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Semiconductor device, manufacturing method thereof and electronic device

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as unfavorable production line monitoring, insufficient windows, and difficult monitoring of cutouts, etc., to reduce soldering Risk of falling balls, increased crafting window, effects of avoiding dropped balls

Active Publication Date: 2018-10-23
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the notch of wafer-level chip-scale packaging products is difficult to monitor. It is usually determined by X-SEM in the early stage of inspection. However, the results of X-SEM are judged by engineers, and there is no clear and quantifiable standard to judge. Depending on experience and carefulness, the wide variety of products may cause the window of some products to be not large enough, and the performance of wet etching is unstable. Therefore, this method is not conducive to the monitoring of the production line, and problems cannot be found in time. ) can only represent the performance of the machine at that time

Method used

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  • Semiconductor device, manufacturing method thereof and electronic device
  • Semiconductor device, manufacturing method thereof and electronic device
  • Semiconductor device, manufacturing method thereof and electronic device

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Embodiment 1

[0049] The following will refer to Figure 2A ~ Figure 2G A method for fabricating a semiconductor device according to an embodiment of the present invention is described in detail.

[0050] The manufacturing method of the semiconductor device of the present embodiment comprises:

[0051] First, a semiconductor substrate 200 is provided, a seed layer 201 is formed on the semiconductor substrate 200, a first patterned photoresist layer 202 is formed on the seed layer, and the first patterned photoresist layer Having a first opening exposing a region where a bottom metal layer is to be formed, forming a bottom metal layer in the first opening, the formed structure is as Figure 2A shown.

[0052] The semiconductor substrate 200 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors etc. or silicon-on-insulator (SOI), silicon...

Embodiment 2

[0074] The present invention also provides a semiconductor device, such as Figure 2G As shown, the semiconductor device includes: a semiconductor substrate 200, on which a seed layer 201A and a bottom metal layer located on the seed layer 201A are formed, and the bottom metal layer includes a first bottom metal layer 203 and a second bottom metal layer 204; a protective layer is formed on the sidewall of the bottom metal layer and the seed layer; a solder ball 209 is formed on the bottom metal layer, and the solder ball 209 surrounds the bottom metal layer layer and is fusion-bonded with the bottom metal layer, wherein the protection layer is made of the same material as the solder ball.

[0075] Wherein the semiconductor substrate 200 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multilayers composed of these semiconductors The structure or the like may be silicon-on-...

Embodiment 3

[0078]Still another embodiment of the present invention provides an electronic device, including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a semiconductor substrate, on which a seed layer and a bottom metal layer above the seed layer are formed; on the sidewall of the bottom metal layer and on the seed layer A protection layer is formed; solder balls are formed on the bottom metal layer. Wherein, the protection layer is made of the same material as the solder ball.

[0079] Wherein, the semiconductor substrate can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayers composed of these semiconductors The structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-...

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Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The manufacturing method comprises the steps of providing a semiconductor substrate, and forminga seed layer on the semiconductor substrate and a bottom metal layer on the seed layer; forming a protective layer on the side wall of the bottom metal layer; removing the part, which is located outside the bottom of the bottom metal layer, of the seed layer, and retaining the part located at the bottom of the bottom metal layer; and setting a solder ball on the bottom metal layer so as to form abump for packaging. The manufacturing method of the semiconductor device can reduce an undercut in the bottom metal layer so as to reduce the dropping risk of the solder ball. The semiconductor device and the electronic device have similar advantages.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] Wafer Level Chip Scale Packaging (WLCSP for short) is a packaging and testing method that first performs packaging and testing on the entire wafer, and then cuts it into individual IC particles. Since the packaged volume is equal to the original size of IC die, wafer-level chip-scale packaging has the advantages of reducing size and increasing speed, and has attracted more and more attention and application. [0003] The wafer-level chip-scale packaging method needs to form bumps (bumps) for packaging on the wafer first. One of the commonly used methods for forming bumps is the ball placement method, which generally forms a seed layer (bump) on the wafer first. seed layer), then define the area of ​​the bottom metal layer (UBM) by photolithography and fo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/492H01L21/02H01L21/60
CPCH01L21/02365H01L23/492H01L24/30H01L2224/26
Inventor 刘瑛
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP