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Semiconductor and formation method thereof

A technology of semiconductor and isolation structure, applied in the field of semiconductor structure and its formation, can solve the problem that the electrical performance of the semiconductor structure needs to be improved, and achieve the advantages of reducing plasma damage in lateral etching, increasing the etching process window, and improving the removal effect. Effect

Active Publication Date: 2018-11-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Application Information

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Problems solved by technology

[0004] However, the electrical performance of prior art semiconductor structures needs to be improved

Method used

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  • Semiconductor and formation method thereof
  • Semiconductor and formation method thereof
  • Semiconductor and formation method thereof

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Experimental program
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Embodiment Construction

[0015] It can be seen from the background art that the electrical performance of the semiconductor structure in the prior art needs to be improved. Analyze the reasons for this:

[0016] In semiconductor manufacturing, with the continuous reduction of feature size, in order to effectively fill the lithography gap of smaller nodes, improve the minimum pitch between adjacent semiconductor patterns, and improve the line width roughness (Liner WidthRoughness) , LWR) and line edge roughness (Liner Edge Roughness, LER), self-alignment process is more and more widely used in fin formation process, such as self-aligned double patterned (Self-aligned Double Patterned, SADP) craft.

[0017] Among them, according to the actual layout (layout) design, the pattern density of each area of ​​the substrate is not exactly the same, and the pattern density of the substrate surface is distinguished, and the substrate includes a pattern dense area (Dense Area) and a pattern sparse area (ISO Area...

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Abstract

The invention relates to a semiconductor structure and a formation method thereof. The formation method comprises the following steps: providing a substrate, wherein the substrate comprises a device area and an isolation area which are adjacent, discrete fin parts are formed on the substrate, and distances between every two adjacent fin parts are equal; forming a protective layer on the side wallof each fin part; etching and removing the protective layer with partial thickness and part of fin parts in the isolation area by adopting a first etching technology; taking the rest of the protectivelayers as a mask, etching the rest of the fin parts in the isolation area by adopting a second etching technology, and forming pseudo fin parts; after the second etching technology is carried out, removing the rest of the protective layers; and after the rest of the protective layers are removed, forming an isolation structure on the substrate, wherein the top of the isolation structure is lowerthan the top of the fin parts in the device area and is higher than the top of the pseudo fin parts. The formation method divides a step of etching the fin parts in the isolation area into two steps,thus the size of an etching process window for removing the fin parts in the isolation area can be increased, and etching damage on adjacent fin parts in the device area is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In the field of semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction of feature size, the channel length of MOSFET field effect transistors is also continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur. [0003] Therefore, in order to better adapt to the reductio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66795H01L29/7853H01L21/31116H01L29/6681H01L21/76232H01L21/3065H01L27/0886H01L21/31111H01L21/3086
Inventor 胡华勇林益世
Owner SEMICON MFG INT (SHANGHAI) CORP