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Terminal structure of power device and fabrication method of terminal structure

A technology of power device and terminal structure, applied in semiconductor/solid-state device manufacturing, electric solid-state device, semiconductor device, etc., can solve the problems affecting device performance, unstable device reliability, etc., to reduce the chip area and reduce the voltage divider ring The effect of enhanced area and pressure resistance

Pending Publication Date: 2018-11-30
江苏丽隽功率半导体有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the low concentration of the extension junction 31 at the P-junction terminal, which is usually the 12th power implant dose, it is very susceptible to the influence of surface charges and process fluctuations, and the reliability of the device is extremely unstable.
[0005] As mentioned above, whether the current conventional field limiting ring technology or the junction terminal expansion technology is used to form the voltage divider structure, it will affect the device performance to a certain extent.

Method used

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  • Terminal structure of power device and fabrication method of terminal structure
  • Terminal structure of power device and fabrication method of terminal structure
  • Terminal structure of power device and fabrication method of terminal structure

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Embodiment Construction

[0053] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0054] This application discloses a terminal structure of a power device and a manufacturing method thereof. The power device can be divided into an active area and a terminal area. The terminal area is also the voltage division area of ​​the background technology, thereby forming an active structure and a terminal structure. The terminal structure of the power device in this application adopts a hybrid junction terminal extension structure, please refer to Figure 4 Shown in the flow chart, the production method comprises the following steps:

[0055] Step S01, providing a substrate 40 with ions of the first conductivity type, and growing an epitaxial layer 41 of ions of the first conductivity type on the substrate 40. The ions of the first conductivity type are N-type ions or P-type ions. In this application, N-type ions are referred to as...

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Abstract

The invention discloses a terminal structure of a power device and a fabrication method of the terminal structure, and relates to the technical field of semiconductors. An annular ring is formed in anepitaxial layer of the fabricated terminal structure of the power device, a shallow junction is formed at a right side of the annular ring, namely a surface at an outer side of a chip, so that a depletion region can be expanded towards the outer side of the chip when a high voltage is applied to a main junction; when the depletion region is expanded to the shallow junction, a power line pointingto a surface can be expanded towards the outer side of the chip by the shallow junction, the power line originally concentrated on the surface of the chip is shared, the voltage-resistant capability of the annular ring is substantially improved compared with a conventional field limitation ring, relatively high voltage resistance can be achieved under the condition of relatively small terminal are, so that the effect of a voltage division ring is maximized, the area of the voltage division ring is reduced, the chip area is reduced, and the device performance is improved; and meanwhile, a separate process is not needed for formation of the shallow junction, the formation of the shallow junction and fabrication of an active region can be synchronously completed, the process difficulty is substantially reduced, and the device cost is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a terminal structure of a power device and a manufacturing method thereof. Background technique [0002] The most important performance of a power device is to block high voltage. The device is designed to withstand high voltage on the depletion layer of the PN junction, metal-semiconductor contact, and MOS interface. As the applied voltage increases, the electric field strength of the depletion layer will also increase. Large, and eventually avalanche breakdown occurs beyond the material limit. The curvature of the electric field increases in the depletion region at the edge of the device, which will cause the electric field strength to be greater than that inside the die, and avalanche breakdown will occur at the edge of the die earlier than inside the die during the voltage increase. Please refer to figure 1 The schematic diagram of the position of each area of ​​the ...

Claims

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Application Information

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IPC IPC(8): H01L27/06H01L29/06H01L29/40H01L21/77
CPCH01L27/0629H01L29/0623H01L29/0684H01L29/404H01L21/77
Inventor 范捷万立宏王绍荣
Owner 江苏丽隽功率半导体有限公司