Method for manufacturing LTPS array substrate
A technology for array substrates and manufacturing methods, which is applied in the field of manufacturing low-temperature polysilicon array substrates, can solve the problems of complex process methods and many layers of films, and achieve the effects of process method optimization, process step reduction, and process time saving
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Embodiment 1
[0042] The present invention provides a manufacturing method of LTPS array substrate, the following combination Figure 2 to Figure 6 The manufacturing method is described in detail.
[0043] As shown in the figure, the manufacturing method includes the following steps:
[0044] Step S10, such as figure 2 As shown, a substrate 201 is provided, and the substrate 201 is usually made of a transparent glass substrate. A metal layer is deposited on the substrate 201, the metal layer is patterned by a photolithography process, and a metal light-shielding layer 202 is formed on the substrate 201. Generally, the material of the metal light-shielding layer 202 is molybdenum aluminum alloy, Chromium, molybdenum or other materials that have both light-shielding function and conductive properties.
[0045] In step S20, a buffer layer 203 is formed on the metal light-shielding layer 202. The material of the buffer layer 203 is silicon nitride, silicon oxide or a combination of both.
[0046] I...
Embodiment 2
[0051] In the first embodiment, the gate line trench is formed by trenching in the formed gate insulating and inter-insulating layer, and then the gate line is formed in the gate line trench to realize the gate line The design in the same layer as the source electrode and the drain electrode has a relatively simple structure and reduces the thickness of the film layer of the array substrate, but requires a process flow of forming the gate trench through exposure, etching, physical vapor deposition, etc.
[0052] Such as Figure 7 As shown, in this embodiment, the manufacturing step of the gate line trench is eliminated. After the steps S10 to S40 as described in the first embodiment, the polysilicon layer 701, the first gate insulating layer and the inter-insulating layer are formed. 702. The second gate insulating and inter-insulating layer 703 and other structures are directly coated with a layer of positive photoresist on the second gate insulating and inter-insulating layer 70...
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