Gate dielectric layer trap state measurement method for insulated gate HEMT

A technology of insulating gate type and gate dielectric layer, which is applied in the field of microelectronics, can solve the problems that the quality of the dielectric layer cannot be determined and the extraction of the dielectric layer cannot be applied, and achieves the effect of high feasibility and guaranteed extraction accuracy

Active Publication Date: 2019-06-18
西安太乙电子有限公司
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Problems solved by technology

[0006] However, this method is only applied to HEMT devices, and cannot be applied to the extraction of the trap state d

Method used

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  • Gate dielectric layer trap state measurement method for insulated gate HEMT
  • Gate dielectric layer trap state measurement method for insulated gate HEMT
  • Gate dielectric layer trap state measurement method for insulated gate HEMT

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Embodiment Construction

[0066] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An AlGaN / GaN heterojunction MIS-HEMT is taken as an example for illustration.

[0067] refer to figure 1 and figure 2 , the common HEMT structure used in the present invention, the structure is from bottom to top: substrate 1, transition layer 2, dielectric layer 3, barrier layer 4 and protection layer 5. refer to image 3 , The MIS-HEMT structure used in the present invention is as follows from bottom to top: substrate 1 , transition layer 2 , dielectric layer 3 , barrier layer 4 , insulating layer 6 and protection layer 5 .

[0068] The method for extracting the internal trap state of the gate dielectric layer in the present invention is as follows:

[0069] Step 1: Carry out the C-V characteristic test on the MIS-HEMT device and HEMT device used, obtain the corresponding C-V curve diagram, and determine the depletion voltage of the corresponding device according to the curve diagram; the C-V characteristic test cu...

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Abstract

The invention discloses a gate dielectric layer trap state measurement method for an insulated gate HEMT. The method is characterized in that a HEMT device is made on the same substrate through masking, depletion voltages of corresponding devices are obtained by performing C-V characteristic tests on the HEMT device and an MIS-HEMT device, a gate voltage is selected by the vicinity of the depletion voltage as a test point voltage, capacitance pair frequency (Cm~ f) and conductance pair frequency (Gm~ f) characteristics are tested under different gate voltages, barrier layer trap state densityof a common HEMT device and MIS-HEMT total trap state density are obtained through model calculation, the dielectric layer trap state density of the MIS-HEMT device is calculated, on the basis, the quality of a dielectric layer can be determined.

Description

technical field [0001] The invention belongs to the field of microelectronic technology, and relates to the problem of extracting the trap state density on the surface of semiconductor devices and gate dielectric layers, especially for high electron mobility transistors with heterojunction structures of III-V compound semiconductor materials, and can be used for such Comparative analysis of the trap state density of the device gate dielectric layer. Background technique [0002] Semiconductor materials composed of group III elements and group V elements, such as gallium nitride (GaN)-based, gallium arsenide (GaAs)-based semiconductor materials, often have large gap widths, so people usually use these III - Group V compound semiconductor materials form various heterojunction structures. The high electron mobility transistor based on the above heterojunction has the characteristics of high carrier mobility, high operating frequency, high power and good radiation resistance, a...

Claims

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Application Information

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IPC IPC(8): G01R31/26
Inventor 毕志伟张璨
Owner 西安太乙电子有限公司
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