Semiconductor device and method of forming the same

Abstract

The invention discloses a semiconductor device and a forming method thereof, and the method comprises the steps: providing a semiconductor substrate which comprises a TFET region and a CMOS region; covering the TFET region by adopting a first covering layer, forming a CMOS lightly-doped drain region in the CMOS region under the protection of the first covering layer, and carrying out first annealing process treatment; removing the first covering layer, and forming a TFET grid side wall and a CMOS grid side wall; forming a source-drain doped region in the TFET region and the CMOS region, and carrying out second annealing process treatment; forming a protective layer covering the CMOS region, removing at least one part of the side wall of the TFET gate under the protection of the protectivelayer, and exposing the semiconductor substrate between the TFET gate and the source-drain doped region of the TFET region; and forming a TFET lightly-doped drain region in the TFET region. Accordingto the scheme, the concentration gradient of the junction surface of the lightly-doped drain region of the TFET can be improved, and the tunneling probability and the on-state current of the device are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] With the development of semiconductor technology, negative effects such as the short channel effect of devices are becoming more and more serious. The impact of the short channel effect can be reduced by replacing a traditional Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a Tunneling Field-effect Transistor (TFET). Due to the excellent sub-threshold characteristics of TFET, the operating voltage can be greatly reduced compared with CMOS, so it is suitable for the field of ultra-low leakage and ultra-low power consumption. Unlike conventional CMOS, the source and drain regions of a TFET are doped differently. [0003] In circuit design, TFETs often need to be matched with standard CMOS devices, so the TFET process and the CMOS process are often set to be comp...

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Problems solved by technology

[0004] In the existing TFET manufacturing process, TFET lightly doped drain (Lightly Doped Drain, LDD) process and CMOS LDD process are carried out before the LDD annealing (Anneal) process, for example, ion implantation process is used before or after the CMOS LDD process TFET LDD is formed, so the dopant ions of TFET LDD will undergo LDD Anneal and the source / drain anneal (Source / Drain Anneal) after the source-drain doped region is formed, because the high temperature in the annealing process will affect the heat of the dopant ions of TFET LDD budget, and reduce the concentration gradient of the TFET LDD junction, which will easily lead to a decrease in the TFET tunneling probability and drive current, and a decrease in the device tunneling probability and on-state current

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