A kind of vcsel chip with high power and preparation method thereof
A high-power, chip technology, applied in the field of VCSEL, can solve the problems of complex manufacturing process, unstable power and high cost, and achieve the effects of increasing the recombination probability, increasing the wave function correspondence, and increasing the number of particles inversion.
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Embodiment 1
[0027] A VCSEL chip with high power, comprising a substrate grown sequentially along the growth direction, an N-type DBR layer, an active layer and a P-type DBR layer, the active layer including a first InGaAs well layer grown sequentially along the growth direction 61. First (In x Al y Ga z ) 0.5 (As m P n ) 0.5 Barrier layer 62, second InGaAs well layer 63, second (In x Al y Ga z ) 0.5 (As m P n ) 0.5 barrier layer 64, the third InGaAs well layer 65 and the third (In x Al y Ga z ) 0.5 (As m P n ) 0.5 The barrier layer 66, wherein 0x Al y Ga z ) 0.5 (As m P n ) 0.5 barrier layer 62, the second (In x Al y Ga z ) 0.5 (As m P n ) 0.5 barrier layer 64 and the third (In x Al y Ga z ) 0.5 (As m P n ) 0.5 The thickness of the barrier layer 66 is 5-20 nm, respectively. The schematic diagram of the structure of the active layer is shown in figure 1 shown.
[0028] The third (In x Al y Ga z ) 0.5 (As m P n ) 0.5 The Al composition in the ...
Embodiment 2
[0033] A kind of preparation method of the VCSEL chip with high power of above-mentioned embodiment 1, comprises:
[0034] growing an N-type DBR layer on the substrate;
[0035] On the N-type DBR layer, a first InGaAs well layer, a first (In x al y Ga z ) 0.5 (As m P n ) 0.5 barrier layer, the second InGaAs well layer, the second (In x al y Ga z ) 0.5 (As m P n ) 0.5 barrier layer, the third InGaAs well layer and the third (In x al y Ga z ) 0.5 (As m P n ) 0.5 Barrier layer, wherein, 0x al y Ga z ) 0.5 (As m P n ) 0.5 barrier layer, the second (In x al y Ga z ) 0.5 (As m P n ) 0.5 base layer and third (In x al y Ga z ) 0.5 (As m P n ) 0.5 The thickness of the barrier layer is respectively 5-20nm; the third (In x al y Ga z ) 0.5 (As m P n ) 0.5 The Al composition in the barrier layer is larger than the second (In x al y Ga z ) 0.5 (As m P n ) 0.5 The Al composition in the barrier layer, the second (In x al y Ga z ) 0.5 (A...
Embodiment 3
[0038] Such as figure 2 As shown, a high-power VCSEL chip includes: a substrate 1, a buffer layer 2, an N-type DBR layer 3, a first confinement layer 4, a first waveguide layer 5, and an active layer 6 stacked in sequence along the growth direction , a second waveguide layer 7, a second confinement layer 8, an oxide layer 9, a P-type DBR layer 10 and a protective layer 11, wherein the substrate 1 is a GaAs substrate, and the buffer layer 2 is a GaAs buffer layer, so The protective layer 11 is a P-GaAs protective layer. The buffer layer 2 has a thickness of 10-25nm; the N-type DBR layer 3 has a thickness of 3-6um, preferably 4um; the first confinement layer 4 and the second confinement layer 8 have a thickness of 40-90nm respectively , preferably 60nm; the thickness of the first waveguide layer 5 and the second waveguide layer 7 are respectively 40-80nm, preferably 50nm; the thickness of the oxide layer 9 is 10-100nm, preferably 100nm; the thickness of the P-type DBR layer 2...
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