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Monitoring structure and monitoring method for critical dimensions of semiconductor process

A key dimension, semiconductor technology, applied in the direction of semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as complex process steps, and achieve the effect of improving performance and yield, improving efficiency and accuracy

Active Publication Date: 2021-07-09
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to improve the reliability and performance of the device, the WAT test during the device preparation process, for example, in-line (Inline) measurement of the formed pattern or the critical dimension (CD) of the component in the key steps of the device, but each layer is generally only Test some components or areas, such as 1-2 film layers, the actual process steps are complicated, and there may be relatively large differences between slices, especially for some very critical levels, such as active area / gate The gate (GT), etc., will directly affect the characteristics of the device. Currently, there is no suitable test pattern (test key) to directly monitor (monitor inline) the fluctuation of critical dimensions. Use the test pattern (test key) to monitor key dimensions key) combined with the characteristics of the device can quickly lock whether there is a deviation in the online critical dimension

Method used

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  • Monitoring structure and monitoring method for critical dimensions of semiconductor process
  • Monitoring structure and monitoring method for critical dimensions of semiconductor process
  • Monitoring structure and monitoring method for critical dimensions of semiconductor process

Examples

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Embodiment 1

[0092] In order to solve the problems existing in the prior art, the present invention provides a monitoring structure for critical dimensions of a semiconductor process. The monitoring structure will be further described below in conjunction with the accompanying drawings. in, Figures 2A-2C It is a structural schematic diagram of the monitoring structure described in this embodiment.

[0093] Specifically, in this embodiment, the critical dimension is monitored by the change of the resistance, wherein the size of the resistance is related to the material, the length, and the size of the interface. In semiconductors, polysilicon (Poly) resistance, diffusion (Diff ) resistors and metal (Metal) resistors, etc., in this embodiment, the formation process of polysilicon (Poly) resistors is used as an example to illustrate:

[0094] First provide a substrate, deposit a layer of polysilicon on the substrate, and then etch out the strip-shaped polysilicon resistance pattern by photo...

Embodiment 2

[0116] Attached below Figures 4A-4B The capacitance-based monitoring structure of the present invention is described.

[0117] First, if Figure 4A As shown, the first test piece includes:

[0118] Base 201;

[0119] A first grid structure 204 is located on the substrate 201 to serve as a first plate of the first test piece;

[0120] The first doped region 203 is located in the substrate 201 on both sides of the first gate structure, and the first doped region together with the substrate 201 under the first gate structure serves as the first doped region. A second plate of a test piece, wherein the overlapping portion of the first plate and the second plate has the first width and the first length;

[0121] The first gate dielectric layer, located between the substrate 201 and the first gate structure, serves as the dielectric of the first test piece, to be in contact with the first electrode plate and the second electrode The plates together form a first capacitor.

[...

Embodiment 3

[0150] Attached below Figure 4A and 4C The capacitance-based monitoring structure of the present invention is described.

[0151] In this embodiment, the first test piece is the same as the first test piece in Embodiment 2, such as Figure 4A As shown, no further details are given here. In this embodiment, the second test piece is as Figure 4C shown, including:

[0152] a second grid structure 204' located on the substrate to serve as a first electrode plate of the second test piece;

[0153] The second doped region 203' is located in the substrate under the second gate structure, and the second doped region and the substrate under the second gate structure serve as the second test The second pole plate of the component, wherein, the second doped region includes at least one of the test strips, for example, the second doped region includes only one of the test strips or the second doped region includes several Test strips arranged at intervals and connectors connecting ...

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Abstract

The invention relates to a monitoring structure and a monitoring method of critical dimensions of a semiconductor process. The test structure includes: a first test piece having a first width, a first length, and a first electrical parameter; a second test piece including at least one test strip, the test strip having a second width and a second length, the The second test piece has a second electrical parameter, wherein the second width is much smaller than the first width, the first length, and the second length, and the design dimension of the second width is a critical dimension of the semiconductor process, according to The first electrical parameter, the first width, the first length of the first test piece and the second electrical parameter and the second length of the second test piece are used to monitor the actual size of the second width, and the second The actual dimension of the width is compared with the design dimension of the second width to determine whether the critical dimension of the semiconductor process has changed. CDs at most key levels can be monitored through the structure and method.

Description

technical field [0001] The present invention relates to the field of semiconductors, and in particular, the present invention relates to a monitoring structure and a monitoring method for critical dimensions of a semiconductor process in a semiconductor process. Background technique [0002] Integrated circuit manufacturing technology is a complicated process, and the technology is updated very quickly. A key parameter that characterizes integrated circuit manufacturing technology is the minimum feature size, that is, critical dimension (CD). The reduction makes it possible to place millions of devices on each chip. [0003] At present, products are thin, light and compact. ICs are becoming smaller and more powerful, and the number of pins is increasing. In order to reduce the area occupied by chip packaging and improve IC performance, flip chip (Flip Chip) packaging is common at this stage. It is used in graphics chips, chipsets, memory and CPUs. The unit price of the ab...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/30
Inventor 孙晓峰秦仁刚盛拓
Owner CSMC TECH FAB2 CO LTD