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A method for improving radiation resistance performance of mos devices or integrated circuits

A technology for MOS devices and integrated circuits, applied in the field of microelectronics reliability, can solve problems such as affecting channel doping distribution, changing gate oxygen trap density/interface quality, affecting device radiation resistance, etc. The effect of improving anti-total dose radiation performance and improving normal performance

Active Publication Date: 2021-08-03
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Since the stress in the channel may affect the doping distribution in the channel, or change the gate oxide trap density / interface quality, etc., it will affect the radiation resistance of the device

Method used

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  • A method for improving radiation resistance performance of mos devices or integrated circuits
  • A method for improving radiation resistance performance of mos devices or integrated circuits
  • A method for improving radiation resistance performance of mos devices or integrated circuits

Examples

Experimental program
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Embodiment

[0031] Example: Prepare 65nm core PMOS devices with different lengths SA of the source-drain diffusion region, and compare their normal performance and anti-total dose radiation performance to verify the effectiveness of the present invention. Specific steps are as follows:

[0032] Step 1. When doing layout design, manually change the size of the length SA of the source and drain diffusion region of the 65nm PMOS device. The schematic diagram of SA is as follows figure 1 As shown, for a device with a gate length of 60 nanometers and a gate width of 200 nanometers, the default SA is equal to 0.18 microns;

[0033] Step 2. Prepare PMOS devices with different SAs using a 65-nanometer standard process;

[0034] Step 3. test and obtain the transfer characteristic curve of the 65 nanometer PMOS device;

[0035] Step 4. extract the threshold voltage of 65 nanometers PMOS device with constant current method, and compare the drain current of different SA devices under the same overd...

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Abstract

The invention discloses a method for improving the anti-irradiation performance of MOS devices or integrated circuits. By utilizing the technological characteristics of the strained silicon technology introduced by nanoscale MOS devices, the length SA of the source-drain diffusion region of PMOS devices is properly adjusted during layout design, and the final increase is achieved. The compressive stress in the large channel can increase the hole mobility in the channel and improve the normal performance of the PMOS device. On the other hand, it can also reduce the threshold voltage drift caused by the total dose irradiation, thereby reducing the impact of the total dose irradiation on the nanometer The impact of nanoscale MOS devices can improve the anti-total dose radiation performance of nanoscale integrated circuits.

Description

technical field [0001] The invention relates to a method for improving the anti-radiation performance of MOS devices or integrated circuits, in particular to the layout design of PMOS devices, and belongs to the field of microelectronic reliability. Background technique [0002] As the technology node of microelectronic devices enters below 90 nanometers, in order to overcome the serious mobility degradation and other problems, strained silicon technology is applied to the manufacture of VLSI. The strained silicon technology introduces stress in the device channel through different process methods to improve the carrier mobility of the channel and thus improve the device performance. For example, for 65nm technology generation devices, taking the capping layer technology as an example, the basic principle is strain memory technology, that is, a certain stress is applied to the device by covering a layer of strain layer on the device. When the annealing temperature exceeds th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/552H01L27/02H01L29/08H01L29/78
CPCH01L23/552H01L27/0207H01L29/0847H01L29/7847H01L29/7848
Inventor 安霞任哲玄李艮松张兴黄如
Owner PEKING UNIV