High-silicon aluminum alloy adapter plate and preparation method thereof

Abstract

The invention discloses a high-silicon aluminum alloy adapter plate and a preparation method thereof. The adapter plate comprises a substrate, a connecting column array and an insulating dielectric layer filled in a gap between the connecting column array and the substrate, the connecting column array is formed by processing the substrate through a laser vertical through hole technology; the substrate and the connecting column array are made of high-silicon aluminum alloy, the insulating dielectric layer is made of a glass dielectric, connecting columns of the connecting column array are coaxial with the insulating dielectric layer, and the connecting columns, the glass dielectric and the substrate have the same height. The adapter plate prepared by adopting the method provided by the invention is firm and reliable in bonding interface and high in air tightness, and the blind hole center connecting column has electrical conductivity and can be directly used for electrical interconnection, so that a through hole metallization process can be omitted, the adapter plate preparation process flow is simplified, and the adapter plate preparation time and cost are reduced.

Description

technical field [0001] The invention belongs to the technical field of microelectronic packaging, and in particular relates to a high-silicon aluminum alloy adapter plate and a preparation method thereof. Background technique [0002] With the upgrading of technology, electronic products continue to develop towards high performance and miniaturization. The interconnection density of electronic packaging is getting higher and higher, and the size is getting smaller and smaller. Micro-assembly technology has developed from two-dimensional to three-dimensional. At present, the cutting-edge packaging technologies in the industry include 2.1D packaging represented by wafer-level packaging (WLCSP) and carrier-level packaging (PLP), 2.5D packaging with interposer technology as the core, and three-dimensional through-silicon via (3D TSV) process for 3D packaging of chip stacks in the Z direction. [0003] At present, because the 3D TSV packaging process is immature in terms of desi...

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Problems solved by technology

[0004] There are problems such as thermal expansion coefficient mismatch between the existing organic matrix interposer board and the chip, large warping deformation, etc., making it difficult to achieve high reliability and high density interconnection

However, the use of glass substrates to prepare interposers has problems such as low processing speed and high cost of through holes. The commonly used DRIE method etches glass through holes at a rate of only 50nm/min. The shape and size of the through holes are limited, and i

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