Small-size three-dimensional anti-fuse FPGA online debugging verification method

Abstract

The invention discloses a small-size three-dimensional anti-fuse FPGA online debugging verification method. According to the method, the miniaturization design requirement is fully considered, an SRAMbased FPGA design is transplanted to more reliable anti-fuse FPGA after a test program is finalized, the influence on a product caused by the phase design change is reduced, and a QFP208 package withanti-fuse FPGA designed internally in a mother board surface mount package in a nested manner. After the debugging of the SRAM type FPGA on a daughter board is completed, the verification circuit isdesoldered, and an anti-fuse FPGA chip can be welded on the internal nested package. According to the invention, the problem that the hardware design is incompatible when the tested FPGA design is transplanted to a more reliable anti-fuse FPGA is solved, the size of averification circuit is effectively reduced, and the influence of the FPGA for debugging on the layout and wiring of a mother boardcircuit is greatly reduced. According to the invention, the requirement for miniaturization design of aerospace products can be met, and the integration level of motherboard circuit design is improved.

Description

technical field [0001] The invention relates to a small-volume three-dimensional antifuse FPGA online debugging verification method, which belongs to the technical field of integrated circuits. Background technique [0002] FPGA (Field Programmable Gate Array Field Programmable Gate Array)) is a high-density programmable logic device, which is a new type of programmable logic device developed and widely used in recent years. It usually includes three types of programmable resources: Programmable logic function block CLB. Programmable I / 0 module lOB and programmable internal interconnection PI. These three parts are programmable in themselves, but also in relation to each other. [0003] Due to the particularity of the space environment, single event upsets (SEUs) occur frequently in orbiting satellite products, and non-volatile FPGA devices based on antifuse have more advantages than ASIC and SRAM products, so designers must consider the use of SRAM-based FPGA designs are...

AI Technical Summary

Problems solved by technology

[0007] The technical solution problem of the present invention is: overcome the deficiencies in the prior art, propose a kind of small-volume three-dimensional anti-fuse FPGA online debugging verification method, solve the problem that the FPGA design based on SRAM is transplanted to a more reliable anti-fuse FPGA When the hardware design is not compatible

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