Delay phase-locked loop circuit, clock signal synchronization method and semiconductor memory

Abstract

The invention provides a delay phase-locked loop circuit, a clock signal synchronization method and a semiconductor memory. The delay phase-locked loop circuit comprises a delay chain, a register, a decoder, a control unit, a copy delay unit and a phase discriminator. The delay chain is used for delaying an input signal; the register comprises setting codes of clock frequency of high-frequency work; the decoder is used for reading a set code to obtain an estimated clock period; the control unit is connected between the decoder and the delay chain and used for setting the initial length of thedelay chain; the copy delay unit is connected with the delay chain and is used for generating a copy delay signal; the phase discriminator is connected with the copy delay unit and the clock signal and is used for outputting a comparison result signal; and the control unit is connected with the phase discriminator and is used for continuously adjusting the length of the access delay chain along the initial length. According to the invention, the estimated clock period is obtained by reading the setting code of the clock frequency of high-frequency work in the register, so the length of the delay chain is quickly adjusted, and the reliability and accuracy of the circuit are ensured.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a delay phase-locked loop circuit, a synchronous clock signal method and a semiconductor memory. Background technique [0002] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section. [0003] Since the operating clock frequency of the DDR (Double Data Rate SDRAM, double-rate synchronous dynamic random access memory) chip will change, it is required that the delay phase-locked loop circuit can always lock the clock quickly and accurately when the operating clock frequency changes. [0004] When the working clock frequency is arbitrarily switched between higher frequency and lower frequency, the working clock period will also change between picoseconds (ps) to nanoseconds (ns), and it is necessary to set a suitab...

AI Technical Summary

Problems solved by technology

When the delay phase-locked loop circuit is operating at a high-frequency clock, the delay chain will be too long and the power consumption will be too high

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