Semiconductor gate structure and preparation method thereof

Abstract

The invention provides a semiconductor gate structure and a preparation method thereof. The filling thickness of the metal gate in a gate trench is reduced to 1 / 7-2 / 5 of the depth of the gate trench,so that the gate resistance is reduced, the device current is increased, and the device performance is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor gate structure and a preparation method thereof. Background technique [0002] As a well-known semiconductor storage device, Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM for short) is currently widely used in various electronic devices. Dynamic random access memory (DRAM) is composed of many repeated memory cells (cells), each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell The cells are electrically connected to each other through a word line (WL for short) and a bit line (BL for short). [0003] In order to improve the integration level of DRAM and speed up the operation speed of components, as well as to meet consumers' demand for miniaturized electronic devices, the design of the channel length of t...

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Problems solved by technology

[0004] In the existing DRAM, the filling thickness of the above-mentioned metal gate 103 in the gate trench is relatively large, for example, it accounts for more than 5 / 13 of the depth of the gate trench, or even exceeds the depth of the gate trench. More than half of the depth of the channel, although this can increase the length of the channel, but at the same time cause the gate resistance to increase and the device current to decrease, which is not conducive to the improvement of device performance

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