Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Fan-out type packaging piece and manufacturing method thereof

A manufacturing method and packaging technology, which are used in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices, etc., can solve problems such as deformation and fracture of passivation layers, high parasitic capacitance and inductance, and short-circuit signals, and achieve improved protection capabilities. The effect of reducing the generation of parasitic capacitance and reducing the number of metal layers

Active Publication Date: 2020-06-19
JOULWATT TECH INC LTD
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the above-mentioned fan-out packaging structure, when there are many input and output ports (I / O) and there is a design where different signal metal layers overlap directly above the chip, the following problems will be brought about: 1. Higher parasitic capacitance and inductance will be introduced ; 2. Crosstalk between different signal layers; 3. The passivation layer is prone to deformation and fracture due to external force, causing the risk of signal short circuit or open circuit

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Fan-out type packaging piece and manufacturing method thereof
  • Fan-out type packaging piece and manufacturing method thereof
  • Fan-out type packaging piece and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0046] See figure 2 , figure 2 is a schematic structural view of the fan-out package in the first embodiment of the present invention. As shown in the figure, the fan-out package 100 includes a substrate 1 , a chip 5 , a molding material 8 , a first redistribution layer 9 , a second redistribution layer 3 , and a plurality of solder balls 11 . The substrate 1 acts as a support for the entire device, and at the same time bears a part of the electrical performance. The substrate 1 is usually a semiconductor material, such as silicon, germanium, selenium, or a compound semiconductor, an organic semiconductor, and the like.

[0047]Chip 5 is fixed on the substrate 1 by bonding layer 2, and this bonding layer 2 preferably uses non-conductive bonding material, such as glass glue, epoxy resin or other non-conductive colloids, as shown in the figure, this bonding layer 2 In addition to bonding the chip 5 and the substrate 1 to one of them, the second redistribution layer 2 is also...

no. 2 approach

[0063] See Figure 4 , Figure 4 is a schematic structural diagram of a fan-out package in the second embodiment of the present invention. As shown, in this embodiment, a fan-out package 110 incorporates two chips 5a and 5b, each chip having at least one TSV 6'. These two chips can be chips with different functions, or chips with the same function, and there needs to be signal transmission between each other, that is, at least one input and output port 7' of the chip 5a needs to be connected to at least one input and output port of the chip 5b superior. According to the gist of the present invention, these input and output ports that need to be interconnected or extracted will be electrically guided to the corresponding bump 4' on the second surface through the TSV 6'.

[0064] In this embodiment, the patterns of the first redistribution layer 9' and the second redistribution layer 3' need to guide the input and output ports 7' on the first surface that need to be electrica...

Embodiment approach 2

[0065] Embodiment 2 provides a package structure of two chips. It should be noted that, for more than two multi-chip packages, it can also be designed according to the gist of the invention without creative labor. The manufacturing method of the second embodiment is basically the same as that of the first embodiment, only when designing the patterns of the first redistribution layer and the second redistribution layer, it needs to be designed according to specific circuit requirements. The points that are the same as those in Embodiment 1 will not be repeated here.

[0066] To sum up, the present invention proposes a new fan-out package and its manufacturing method. The package introduces a TSV structure into the chip to electrically guide part of the input and output ports to the back, and then connects the front and back sides of the package. The redistribution layer structure is designed to reduce the number of redistribution layer metal layers on a single side, thereby red...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a fan-out type packaging piece and a manufacturing method thereof. A TSV structure is introduced into the chip, a part of input and output ports are electrically guided to a back surface, and then the redistribution layer structures are designed on a front surface and the back surface such that the number of metal layers of a redistribution layer on a single side is reduced,the parasitic capacitance and signal crosstalk are reduced, and the stability and reliability of the device are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a fan-out package and a manufacturing method thereof. Background technique [0002] In the field of semiconductor packaging, with the requirement of high integration of packaging, 3D IC packaging with Through Silicon Via (TSV) as the core has become an important technology in the field of high-density packaging. [0003] At the same time, as chips become smaller and the number of I / Os increases, fan-in wafer-level packaging can no longer meet the requirements for interconnection. As a solution to this contradiction, fan-out (fanout) packaging technology restructures the arrangement of chips in wafers to lead the small chip I / O out of the body to form a larger package. [0004] One of the above-mentioned fanout schemes is chip-on-chip first, and the chip faces down. When there are many I / Os on the front of the chip, it is inevitable that different signal metal layers overl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/48H01L23/485H01L21/60
CPCH01L23/481H01L23/4824H01L24/03H01L2224/02331H01L2224/02379H01L2224/02381H01L2224/0231H01L2224/16225H01L2224/18H01L2224/73253H01L2224/73204H01L2924/15311H01L2224/32225H01L2924/16195H01L2924/00
Inventor 孟繁均陆阳
Owner JOULWATT TECH INC LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com