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Forming method of step structure of 3D NAND, 3D NAND memory and manufacturing method of 3D NAND memory

A 3DNAND and manufacturing method technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of shrinking, unfavorable device size, increasing the occupied area of ​​the step area, etc., so as to reduce the occupied area and reduce the word line layer. Risk of short circuit, effect of size reduction

Active Publication Date: 2020-07-10
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As a result, the occupied area of ​​the step region on the substrate is increased, which is not conducive to the reduction of device size

Method used

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  • Forming method of step structure of 3D NAND, 3D NAND memory and manufacturing method of 3D NAND memory
  • Forming method of step structure of 3D NAND, 3D NAND memory and manufacturing method of 3D NAND memory
  • Forming method of step structure of 3D NAND, 3D NAND memory and manufacturing method of 3D NAND memory

Examples

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Embodiment 1

[0114] This embodiment provides a method for forming a step structure of a 3D NAND memory, such as image 3 As shown, the method includes the following steps:

[0115] Step S101: providing a substrate on which a stack structure is formed, and the stack structure includes a plurality of core regions and step regions located on both sides of the core region;

[0116] Reference Figure 4 and Figure 5 , First provide a substrate 100, the substrate 100 in the first direction namely Figure 5 The X direction and the second direction shown are Figure 5 A plane is formed in the Y direction shown. Along the third direction above the substrate 100 Figure 4 The Z direction shown forms a stacked structure 101, which is formed by alternately arranging insulating layers 1011 and sacrificial layers 1012. In this embodiment, the substrate 100 may be silicon, single crystal silicon-on-insulator or other suitable materials. The insulating layer 1011 in the stacked structure can be silicon oxide,...

Embodiment 2

[0131] This embodiment provides a 3D memory manufacturing method, such as Picture 10 As shown, the method includes the following steps:

[0132] Step S201: forming a step structure in the stacked structure of the substrate according to the method for forming the step structure described in the foregoing embodiment;

[0133] Formed according to the method described in Example 1 Figure 8 with Picture 9 For the step structure shown, the method will not be described in detail here.

[0134] Step S202: forming a storage structure in the core area;

[0135] Such as Picture 11 Shown, formed Figure 8 with Picture 9 After the stepped structure shown, the memory structure 106 is formed in the core regions 1021 and 1022.

[0136] First, like Picture 12 Shown in Picture 11 The cross-sectional view at the position shown by the center line L2-L2 is taken as an example. First, the stack structure 101 on the substrate is etched to form a channel hole 1060 penetrating the stack structure. In a ...

Embodiment 3

[0148] This embodiment provides a 3D NAND memory, which can also be referred to Figure 4 ~ Figure 9 as well as Figure 11 ~ Figure 18 , The memory includes:

[0149] A substrate; a stacked structure formed on the substrate, the stacked structure including a plurality of core regions, and step regions located on both sides of the core region; partition steps formed in the step region; formed in adjacent The first part and the second part of the partition step between the two core regions, the first part and the second part are respectively connected with two adjacent core regions; formed in the A storage structure in the core region; and a common source penetrating the stack structure, the common source penetrating the stack structure.

[0150] Reference Figure 14 ~ Figure 18 , The substrate 100 in the first direction is Figure 5 The X direction and the second direction shown are Figure 5 A plane is formed in the Y direction shown. Along the third direction above the substrate...

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Abstract

The invention provides a forming method of a step structure, a 3D NAND memory and a manufacturing method of the 3D NAND memory. In the forming process of the step structure and the 3D NAND memory, a plurality of core regions and step regions are formed in the stacked structure, a plurality of partition steps are formed in the step regions, and a first part and a second part which are arranged in astaggered mode and insulated from each other are formed on each partition step between every two adjacent core regions. Therefore, the same step area comprises step structures which are respectivelycommunicated with the two adjacent core areas. The occupied area of the step structure on the substrate is reduced, so that the size of each storage unit on the substrate can be reduced, and meanwhile, the number of the storage units on the substrate can be increased. An isolation structure is arranged between the partition steps between every two adjacent core regions, the isolation structures are connected with the word line isolation layers in the common sources, insulation of the first parts and the second parts in the partition steps is achieved, the risk of short circuit of the word linelayers in the two core regions is reduced, and the product yield is increased.

Description

Technical field [0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for forming a 3D NAND step structure, a 3D NAND memory and a manufacturing method thereof. Background technique [0002] As the feature size of devices in integrated circuits continues to shrink, 3D memory technology that stacks multiple planar memory cells to achieve greater storage capacity and lower cost per bit has become more and more popular. 3D memory is a technology for stacking data units. Currently, it is possible to stack data units of more than 32 layers, even 72 layers, 96 layers, 128 layers or more. The vertical storage structure of a 3D storage device is formed by stacking multiple layers of dielectric films, and the word line layer in it needs to be led out via word line contacts. In the prior art, step regions are usually formed on both sides of the memory array, and contacts of each word line layer are formed on the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11565H01L27/1157H01L27/11582H10B43/10H10B43/27H10B43/35
CPCH10B43/10H10B43/35H10B43/27
Inventor 张磊汤召辉周玉婷曾凡清
Owner YANGTZE MEMORY TECH CO LTD
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