Process for generating multi-step trench transistor using polymer isolation layer

Abstract

The invention discloses a process for generating a multi-step trench transistor by using a polymer isolation layer. The process comprises the steps of S1 etching a first trench on a silicon wafer substrate; S2 performing oxidation operation on a primarily processed transistor, and generating a silicon oxide protection layer on the inner side wall of the first trench; S3 depositing and forming an organic silicon film layer on the silicon oxide protection layer of the first trench by a spin coating method; S4 carrying out plasma treatment by using fluorine-containing gas; S5 continuously etchingthe Si layer of the silicon wafer substrate downwards at the bottom of the first trench; S6 removing the organic silicon thin film layer at the bottom of the first trench by adopting a wet etching process; and S7 taking the second trench as a substrate, and continuing to repeat the steps S2 to S6, so that the plurality of trenches are in a multi-step shape in sequence. The design structure of theplurality of trenches obtains a larger transistor area in the same packaging volume, so that the quiescent current passing capacity and the high voltage bearing capacity are improved, and the maximized effective transistor area can be improved by more than three times.

Description

Technical field [0001] The invention belongs to the technical field of wafer production, and specifically relates to a process for generating a multi-step trench transistor by using a polymer isolation layer. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid development. In the development of IC, the functional density (that is, the number of interconnected devices per chip area) is generally increased, while the geometric size (that is, the smallest device or interconnection line that can be manufactured using a manufacturing process) is reduced. The improvement of IC performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase its speed. The advantage of this scaled-down process is to increase production efficiency and reduce related costs. At the same time, this scaled-down process also increases the complexity of processing and manufacturing ICs. [0003] Currently, MOS-FET and...

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Problems solved by technology

[0004] Aiming at the deficiencies of the prior art, the object of the present invention is to provide a process for forming multi-step trench transistors by using a polymer isolation layer, which solves the problem of the limited conduction capability and high voltage carrying capacity of single trench transistors in the prior art. technical issues

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