Chip packaging preprocessing method and chip analysis method

Abstract

The invention provides a chip packaging preprocessing method and a chip analysis method, and belongs to the technical field of integrated circuits. The preprocessing method comprises the following steps of detecting the projection areas of different bare dies on the surface of the multi-chip package; protecting the multi-chip package outside the surface projection area of the bare chip to be removed; corroding the multi-chip package; and stripping the bare die to be removed to obtain an exposed target bare die. The methods are used for FIB pretreatment.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a pretreatment method for multi-chip packaging, a reaction adhesion medium solution, a gold corrosion solution and a chip analysis method. Background technique [0002] As the chip integration becomes higher and higher, there are usually two or more chips inside the chip package. In order to save the chip area, a stacked package is usually used. [0003] In chip failure analysis and chip revision testing, most of them need to use FIB (Focused Ion Beam) to analyze chip failure mechanism and chip circuit repair. In a multi-chip package, the master Die (main die) is the core chip, and the slave die (slave die) are mostly auxiliary chips such as storage and switches. FIB preprocessing is a means to maintain chip pin connectivity and expose all chips under test. In the multi-chip package, since the slave Die is bonded to the main Die, most of the area of ​​the main Die i...

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a chip packaging pretreatment method and a chip analysis method to solve technical problems such as difficult to remove the bare die to be removed and retain the intact target die before chip analysis

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