Field effect transistor with ultra-low power consumption and preparation method thereof

Abstract

The invention provides a field effect transistor with ultra-low power consumption and a preparation method thereof, and belongs to the technical field of field effect transistors. According to the field effect transistor disclosed by the invention, LiNbO3 with good ferroelectricity and stability is innovatively used as a ferroelectric grid material; and different from existing conventional ferroelectric materials such as HfZrO2, PVDF and PZT, the field effect transistor based on the LiNbO3 material has the ultra-low sub-threshold property and further has the stable transfer property of small hysteresis.

Description

technical field [0001] The invention belongs to the technical field of field effect transistors, in particular to a negative capacitance field effect transistor with ultra-low power consumption based on two-dimensional semiconductor materials and a preparation method thereof. Background technique [0002] At present, the main frequency of computers is stagnant, and the degree of integration and energy consumption are the two major limiting reasons. First of all, improving the performance of electronic devices requires transistors with smaller channels, which in turn increases the integration of chips. However, Moore's Law is approaching the limit. As the channels of electronic devices shrink, the channel length is shortened to a few nanometers, and the short channel effect It is very significant; secondly, as the integration level of the chip increases, the heat dissipation energy of the chip will increase. Therefore, how to manufacture electronic devices with better perfor...

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Problems solved by technology

However, in recent years, the subthreshold swing of most negative capacitance transistors has been limited to 30-60mV / dec, such as: A.Rusu (A.Rusu, G.A. Salvatore, D.Jimenez, A.M.Ionescu, in Int. Electron Devices Meet. (IEDM), 2010, 1631.) et al. used PVDF as a ferroelectric material to achieve a minimum SS of Si-based MOSFET of 46mV / dec; Y.Zhao (Y.Zhao, Z.Liang, Q.Huang, C .Chen, M.Yang, Z.Sun, K.Zhu, H.Wang, S.Liu, T.Liu, Y.Peng, G.Han, R.Huang, IEEE Electron Device Lett.2019, 40, 989.) etc. People use HZO as ferroelectric material to construct negative capacitance tunneling transistors, and achieve the lowest SS of 44mV / dec, but it is difficult to obtain transistor devices with ultra-low sub-threshold swing (<10mV / dec)

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