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Manufacturing method of self-aligned metal layer, semiconductor device and electronic device

A metal layer, self-aligned technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of device performance improvement obstacles, unfavorable metal layer process realization, and relaxation of design rules and conditions. , to achieve the effect of friendly structure size and uniformity, improve the range of overlay deviation, and improve the robustness of the process

Active Publication Date: 2020-12-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, it is inevitable that when A and B are transferred to the target thin film coating, defects such as too narrow size or connected line ends will occur, which seriously restricts the process yield.
[0005] In addition, the above process method requires that the distance between the design rules A and B should not be too small, which relaxes the design rule conditions and hinders the performance improvement of some devices.
[0006] In addition, based on the technology of self-aligned double pattern imaging technology and multiple cutting process, there is the possibility of using at least three masks, and the self-aligned double pattern imaging technology has greater constraints on the design rules, which is often not conducive to use on both sides. To the process realization of the metal layer

Method used

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  • Manufacturing method of self-aligned metal layer, semiconductor device and electronic device
  • Manufacturing method of self-aligned metal layer, semiconductor device and electronic device
  • Manufacturing method of self-aligned metal layer, semiconductor device and electronic device

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Embodiment Construction

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0036] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention provides a manufacturing method of a self-aligned metal layer, a semiconductor device and an electronic device. The method comprises the following steps: performing process manufacturability splitting on a design mask of a metal layer; providing a substrate, wherein the substrate comprises a target film layer for manufacturing a metal layer; forming a first structure pattern on the target thin film layer by using the first sub-mask, and forming a side wall by attaching to the side wall of the first structure pattern; performing photoetching and etching by using the second sub-mask, and forming a corresponding second structure pattern on the mask coating where the first structure pattern is located based on a self-alignment effect; removing the first structure pattern, and leaving the side wall and the second structure pattern; patterning the target thin film layer by taking the side walls and the second structure pattern as masks; and forming a metal layer in the patterned target thin film layer. According to the scheme, the side wall process is applied after the first photoetching, so that the minimum distance between multiple photoetching patterns is effectively protected, the overlay deviation of the metal layer is reduced, and the process manufacturing yield is improved.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuits, in particular to a method for manufacturing a self-aligned metal layer, a semiconductor device and electronic equipment. Background technique [0002] Multiple lithography process technology refers to the method that the core design layer of the chip cannot be realized at one time using a lithography machine, but must be used two or more times. For the metal layer, especially the metal layer designed in two directions, when one photolithography cannot satisfy the production of the core layer, two or more photolithography etching techniques must be used, which is called LELE, or LEn, where n Identifies the number of times the LE process was used. Taking LELE technology as an example, its implementation method is as follows; [0003] First, split the core layer into mask A and mask B, and the two masks carry different design layers respectively. Secondly, use mask A to perfo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L23/498
CPCH01L21/4846H01L23/49838
Inventor 张利斌韦亚一冯耀斌
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI