NAND memory and manufacturing method thereof

Abstract

The invention provides an NAND memory and a manufacturing method thereof. The manufacturing method of the NAND memory comprises the steps that a substrate is provided, word lines and selection tubes which are arranged repeatedly are formed on the substrate, and first side walls are formed on the side walls of the word lines and the selection tubes; the first side walls between the adjacent selection tubes are etched to enable the upper surfaces of the first side walls between the adjacent selection tubes to be lower than the upper surfaces of the selection tubes; an interlayer dielectric layeris formed, wherein the interlayer dielectric layer covers the first side wall and the substrate between the adjacent selection tubes; the first side walls between the word lines and between the wordlines and the selection tubes are removed; and oxide layers are formed on the word lines, the selection tube and the interlayer dielectric layer so as to form air gaps among the word lines. The firstside walls between the adjacent selection tubes are partially etched before the interlayer dielectric layer is formed, so that the first side walls between the selection tubes are buried under the subsequently formed interlayer dielectric layer, the selection tubes are prevented from being removed in the process of forming the air gap, and holes are prevented from appearing in the interlayer dielectric layer.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a NAND memory and a manufacturing method thereof. Background technique [0002] As a non-volatile memory, NAND memory has the advantages of large capacity, fast erasing and writing speed, and low cost. It is widely used in consumer, automobile, industrial electronics and other fields. With the development of semiconductor technology, the word line size of NAND memory is continuously shrinking to increase the data storage capacity and meet the actual use requirements. In the prior art, a NAND memory array is usually composed of multiple blocks, and each block includes several word lines and selection transistors. The select transistors are located at both ends of each block and adjacent to the word lines. NAND memory with a word line size below 30nm usually adopts an air gap technology (Air gap) between word lines to reduce the coupling effect between word lines. [0003...

AI Technical Summary

Problems solved by technology

[0003] However, in the manufacturing process of commonly used NAND memory, while air gaps are formed between word lines, voids will appear in the interlayer dielectric layer (ILD). Affect the connection of the metal contact hole, thus affecting the normal use of the device

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