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Semiconductor device

A semiconductor and insulator layer technology, applied in the field of insulator nanosheet devices, can solve problems such as current leakage and surface scattering

Pending Publication Date: 2020-12-29
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the reduction in gate length can lead to short channel effects such as current leakage, surface scattering, velocity saturation, impact ionization, threshold voltage variations, and / or hot carrier effects

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

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Embodiment Construction

[0079] The ensuing disclosure provides many different implementations or examples for achieving different features of the presented subject matter. Specific embodiments of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the ensuing description, a first feature is formed on or over a second feature, may include embodiments where the first and second features are formed in direct contact, and may also include that additional features may be formed on the first feature. and the second feature, so the first and second features may not be in direct contact. In addition, the present disclosure may repeat numbers and / or letters in various embodiments. Such repetition is for simplicity and clarity and does not imply a relationship between the various embodiments and / or configurations discussed.

[0080]In FinFET devices, the reduced gate length makes MOSFETs s...

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Abstract

Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. Aburied insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

Description

technical field [0001] The techniques described in this disclosure relate generally to electronic systems, and more specifically to increasing the read margin of electronic devices using partially buried insulator (BI) nano-sheet devices. Background technique [0002] Metal oxide semiconductor field effect transistors (MOSFETs) are semiconductor devices commonly used in both digital and analog circuits, including static random access memory (SRMA) devices. Metal oxide semiconductor field effect transistors are commonly used to switch and amplify electronic signals within electronic devices. A typical MOSFET includes source, drain, and gate electrodes. Energization of the gate electrode causes current to flow from the source through a channel region to the drain. The gate electrode is characterized by channel length and width. As electronic devices become smaller and smaller, the size of the channel length of MOSFETs is reduced. However, such a reduction in channel length...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/78H01L27/11
CPCH01L29/7838H01L29/0649H01L29/0665H10B10/12B82Y10/00H01L29/0673H01L29/1079H01L29/42392H01L29/66439H01L29/775H01L29/78696H01L27/0207H10B10/125H01L29/66795H01L29/785
Inventor 萧锦涛邱奕勋
Owner TAIWAN SEMICON MFG CO LTD