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Ultraviolet light-emitting diode epitaxial wafer and manufacturing method thereof

A technology for light-emitting diodes and a manufacturing method, which is applied to electrical components, circuits, semiconductor devices, etc., can solve the problems of increased V-shaped pit density, weakened carrier confinement capability, and reduced potential barrier height.

Inactive Publication Date: 2021-02-05
HC SEMITEK SUZHOU
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

When the opening of the V-shaped pit is too large, the barrier height of the inclined surface of the V-shaped pit is reduced, and the ability to confine the carriers is weakened, which will lead to non-radiative recombination between electrons and holes, which will reduce the internal quantum luminous efficiency of the LED.
At the same time, under low temperature conditions, the density of the formed V-shaped pits will gradually increase, resulting in a decrease in the crystal quality of the epitaxial layer.

Method used

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  • Ultraviolet light-emitting diode epitaxial wafer and manufacturing method thereof
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  • Ultraviolet light-emitting diode epitaxial wafer and manufacturing method thereof

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Embodiment Construction

[0027] In order to make the purpose, technical solution and advantages of the present disclosure clearer, the implementation manners of the present disclosure will be further described in detail below in conjunction with the accompanying drawings.

[0028] figure 1 It is a schematic structural diagram of an ultraviolet light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure, as shown in figure 1 As shown, the ultraviolet light emitting diode epitaxial wafer includes a substrate 1 , a buffer layer 2 , an undoped AlGaN layer 3 , an N-type layer 4 , an active layer 5 and a P-type layer 6 stacked on the substrate 1 in sequence.

[0029] The UV light emitting diode further includes a stress release layer 7 disposed between the N-type layer 4 and the active layer 5 , and the stress release layer 7 includes a first sub-layer 71 , a second sub-layer 72 and a third sub-layer 73 stacked in sequence. The first sublayer 71 is a low temperature InGaN subla...

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Abstract

The invention provides an ultraviolet light-emitting diode epitaxial wafer and a manufacturing method thereof, and belongs to the technical field of semiconductors. The ultraviolet light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped AlGaN layer, an N-type layer, an active layer and a P-type layer which are stacked on the substrate in sequence, and further comprises a stress release layer arranged between the N-type layer and the active layer, the stress release layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked, the first sub-layer is a low-temperature InGaN sub-layer, the second sub-layer is a variable-temperature AlInGaN layer, and the third sub-layer is a high-temperature AlGaN layer. The ultraviolet light-emitting diode epitaxial wafer can optimize the opening size of the V-shaped pit, improve the internal quantum light-emitting efficiency of the LED and improve the crystal quality of theepitaxial wafer.

Description

technical field [0001] The disclosure relates to the technical field of semiconductors, in particular to an epitaxial wafer of an ultraviolet light emitting diode and a manufacturing method thereof. Background technique [0002] Short-wavelength ultraviolet light-emitting diodes based on AlGaN materials have a wide range of applications and are an important research content in the field of nitride semiconductor research. [0003] Epitaxial wafers are an important component in the manufacture of light-emitting diodes. The existing ultraviolet light-emitting diode epitaxial wafer includes a substrate, a buffer layer, an undoped AlGaN layer, an N-type layer, an active layer and a P-type layer stacked on the substrate in sequence. Among them, an InGaN stress release layer is usually grown between the N-type layer and the active layer to release the underlying stress and reduce the generation of dislocations. [0004] The stress release layer in the prior art is usually grown u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L33/12H01L33/14H01L33/00
CPCH01L33/007H01L33/12H01L33/145
Inventor 乔楠李昱桦刘源
Owner HC SEMITEK SUZHOU
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