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Chip mounting and packaging structure and method

A packaging method and packaging structure technology, which is applied to semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problem that the adhesive fixed layer is difficult to take into account stress buffering and structural strength, etc., so that it is not easy to move and increase packaging Structural strength and uniform thickness

Inactive Publication Date: 2021-02-26
GUANGHUA LINGANG ENG APPL & TECH R&D (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a die-attach package structure and method, which is used to solve the problem that the adhesive glue fixing layer of the mount-and-place package in the prior art is difficult to take into account both stress buffering and structural strength. question

Method used

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  • Chip mounting and packaging structure and method
  • Chip mounting and packaging structure and method
  • Chip mounting and packaging structure and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0095] Embodiment 1: Die-attach packaging structure with height control layer

[0096] see Figure 3 to Figure 6 , an embodiment of the present invention provides a die-attach package structure, which is characterized in that it includes:

[0097] Substrate 202;

[0098] chip 201, the lower surface of which is pasted on the upper surface of the substrate 202 by adhesive;

[0099] Adhesive glue fixed layer 203, which is formed by curing the adhesive glue;

[0100] a height control layer structure 204, which is formed on the upper surface of the substrate 202 or the lower surface of the chip 201;

[0101] The bonding wire 205 is electrically connected to the chip 201 and the substrate 202 .

[0102] Such as image 3 As shown, it is a die-attach package structure provided by this embodiment. Wherein, the chip 201 may be a stress-sensitive chip such as a pressure sensor with a cavity structure, which is pasted on the upper surface of the substrate 202 by an adhesive. In thi...

Embodiment 2

[0109] Embodiment 2: Chip placement packaging method in which the height control layer structure is formed on the upper surface of the substrate

[0110] Such as Figure 7 to Figure 12 As shown, the present embodiment provides a chip placement and packaging method, which is characterized in that it includes the following steps:

[0111] 1) providing a substrate 302 and a chip 301;

[0112] 2) forming a height control layer structure 304 on the upper surface of the substrate 302;

[0113] 3) coating an adhesive 303a on the substrate 302;

[0114] 4) Paste the lower surface of the chip 301 on the upper surface of the substrate 302 through the adhesive;

[0115] 5) curing the adhesive glue 303a to form the adhesive glue fixed layer 303;

[0116] 6) Form bonding wires 305 on the upper surface of the chip 301 .

[0117] In step 1), see Figure 7 In step S1, a substrate 302 and a chip 301 are provided.

[0118] In step 2), see Figure 7 The S2 step and Figure 8 , forming a...

Embodiment 3

[0124] Embodiment 3: Chip placement packaging method in which the height control layer structure is formed on the lower surface of the chip

[0125] Such as Figure 13 to Figure 18 As shown, the present embodiment provides a chip placement and packaging method, which is characterized in that it includes the following steps:

[0126] 1) providing a substrate 402 and a chip 401;

[0127] 2) forming a height control layer structure 404 on the lower surface of the chip 401;

[0128] 3) coating the adhesive 403a on the substrate 402;

[0129] 4) Paste the lower surface of the chip 401 on the upper surface of the substrate 402 through the adhesive;

[0130] 5) curing the adhesive 403a to form an adhesive fixed layer 403;

[0131] 6) Form bonding wires 405 on the upper surface of the chip 401 .

[0132] In step 1), see Figure 13 In step S1, a substrate 402 and a chip 401 are provided.

[0133] In step 2), see Figure 13 The S2 step and Figure 14 , forming a height control ...

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Abstract

The invention provides a chip mounting and packaging structure and method. The chip mounting and packaging structure comprises: a substrate; a chip, wherein the lower surface of the chip is adhered tothe upper surface of the substrate through an adhesive; an adhesive fixing layer formed by curing the adhesive; a height control layer structure formed on the upper surface of the substrate or the lower surface of the chip; and a bonding lead wire electrically connected with the chip and the substrate. According to the invention, the height control layer structure is arranged between the substrate and the chip, so that the thickness of the adhesive fixing layer is kept uniform; and the introduction of the height control layer increases the packaging structure strength of the chip in the vertical direction, guarantees that the chip is not liable to move in the vertical direction while the introduction of the thicker adhesive fixing layer reduces the thermal stress exerted on the chip by the substrate in the plane direction, and prevents the yield of subsequent technologies of ultrasonic lead bonding of the chip from being reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip placement packaging structure and method. Background technique [0002] Stick-and-place packaging is a widely used form of chip packaging. It achieves the fixation of the chip and the substrate by coating the chip adhesive on the substrate, attaching the chip and heating and curing the adhesive. Die-attach packaging has the advantages of simple and controllable process and low cost. [0003] At present, in the die-attach package, due to the difference in thermal expansion coefficient between the substrate and the chip, the adhesive not only plays the role of bonding and fixing the chip, but also acts as a stress buffer layer between the substrate and the chip to reduce the heat dissipation of the substrate. The impact of expansion and contraction on the thermal stress of the chip. Chips that are sensitive to stress may fail under high thermal stress. An ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/14H01L23/18H01L23/48
CPCH01L23/14H01L23/18H01L23/48H01L2224/83192H01L2224/73265H01L2224/48091H01L2224/8314H01L2924/00014
Inventor 卢基存周华
Owner GUANGHUA LINGANG ENG APPL & TECH R&D (SHANGHAI) CO LTD
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