Formation method of NOR FLASH

Abstract

The invention provides a formation method of NOR FLASH, which comprises the following steps of: providing a substrate which comprises a flash memory region and a logic region which are adjacent to each other; sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are all formed on the flash memory region and the logic region; etching the nitride layer, the floating gate layer and the flash memory oxide layer sequentially to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide; removing the nitride layer of the flash memory region, carrying out ion implantation and annealing on the floating gate layer of the flash memory region and the floating gate layer of the logic region, and part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory region; and removing the interlayer dielectric layer and the floating gate layer in the logic region to form a gate structure of the flash memory region. According to the invention, the area of the flash memory unit is reduced, and the erasing is uniform.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming NOR FLASH. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, electrical programmability and easy erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, with the maturity of new technology nodes, flash memory cells are urged to be produced with high-node technologies. It means that the size of the flash memory unit needs to be reduced. However, reducing the width of the active region and the length of the channel of the flash memory unit will affect the performance of the flash memory unit. [0003] At present, the lateral reductio...

AI Technical Summary

Problems solved by technology

Due to the reduced area, the number of silicon dioxide silicon valleys produced by doping phosphorus contained in the interface between the floating gate and the silicon dioxide in the flash memory oxide layer in each flash memory cell is reduced, which reduces the uniformity of erasing

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