VPX-based CAN and 1553b dual-redundancy architecture design method
A design method, dual-redundancy technology, applied in the field of dual-redundancy hardware structure of CAN and 1553b, to achieve the effect of improving stability and reliability
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[0035] The present invention will be further described in detail with reference to the accompanying drawings and embodiments.
[0036] The present invention designs a completely dual-redundant CAN and 1553b bus communication architecture, and proposes a link self-check and link switching method based on this dual-redundant architecture, thereby improving the link stability of CAN and 1553b and robustness.
[0037] The overall architecture of the system proposed in this design is as follows: figure 1 shown. The present invention takes Figure 2-Figure 5 An implementation scheme of a dual-redundant architecture is shown as an example, and the implementation scheme of link self-checking and link switching of the present invention is introduced in detail.
[0038] Step 1: In this design, two XC7Z045ffg676 chips are used as the main processor and coprocessor of the system, such as figure 2 shown. Let U1 be the main processor, and U2 be the coprocessor.
[0039] Step 2: Since...
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