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Semiconductor assembly

A semiconductor and assembly technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., which can solve the problems of disconnection and unreliable flip-chip assemblies.

Pending Publication Date: 2021-06-29
BRIDGE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The warpage caused by the mismatch of the coefficient of thermal expansion (CTE) may lead to disconnection between the semiconductor chip 15 and the circuit layer 13 on the resin layer 11, thus causing an unreliable flip-chip assembly, especially for very large die or Ultra-Small Bump Assembly (See US Patent Nos. 9,185,799 and 10,068,812)

Method used

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  • Semiconductor assembly
  • Semiconductor assembly
  • Semiconductor assembly

Examples

Experimental program
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Embodiment 1

[0031] Figure 2-Figure 9 It is a diagram of a manufacturing method of a semiconductor assembly in the first embodiment of the present invention, the semiconductor assembly includes a first wiring structure, a second wiring structure and a semiconductor chip.

[0032] figure 2 It is a cross-sectional view of the first wiring structure 201 detachably attached to the sacrificial carrier 30 . The first wiring structure 201 can be directly formed on the sacrificial carrier 30 through a build-up process. The sacrificial carrier 30 can be made of any peelable or removable material, such as silicon, copper, aluminum, iron, nickel, tin or alloys thereof. In this embodiment, the first wiring structure 201 is shown as a multi-layer build-up circuit, which includes multiple layers of dielectric layers 21 and multiple layers of conductive layers 23 formed alternately. The innermost layer of the conductive layer 23 extends laterally on the sacrificial carrier 30 , while the other layer...

Embodiment 2

[0044] Figure 12-Figure 14 It is a diagram of the fabrication method of the semiconductor assembly according to the second embodiment of the present invention.

[0045] For the purpose of brief description, any descriptions in the above-mentioned embodiment 1 that can be used for the same application are incorporated here, and it is not necessary to repeat the same descriptions.

[0046] Figure 12 is a cross-sectional view of the second wiring structure 403, which is similar to Figure 5 The structure shown, but the difference is that the core layer 43 has a vertical connection piece 437, and a plurality of adjustment pieces 453 are distributed in the resin adhesive 451 to form a modified joint matrix 40 on the peripheral sidewall of the warping balance piece 41 and the core layer 43 in the gap between the inner side walls. The coefficient of thermal expansion (CTE) of the adjusting member 453 is usually lower than that of the resin adhesive 451 to effectively reduce the ...

Embodiment 3

[0052] Figure 17 It is a sectional view of the semiconductor assembly according to the third embodiment of the present invention.

[0053] For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

[0054] The semiconductor assembly of this embodiment is similar to Figure 14 The structure shown is different in that the top buildup layer 46 of the second wiring structure 405 further includes a top continuous interlaced fiber sheet 462 blended in the innermost top bonding resin 461, and the bottom buildup layer 47 of the second wiring structure 405 It further includes a bottom continuous interlaced fiber sheet 472 blended in the innermost bottom bonding resin 471 . The continuous interlaced fibers may be carbon fibers, silicon carbide fibers, glass fibers, nylon fibers, polyester fibers or polyamide fibers. More specifically, the top c...

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Abstract

A semiconductor assembly includes a semiconductor chip, a first wiring structure and a second wiring structure. The second wiring structure includes a warp balancer, a core layer, a top build-up layer and a bottom build-up layer. The warp balancer is laterally surrounded by the core layer and preferably has an elastic modulus higher than 100 GPa. The top and the bottom build-up layers are electrically connected to each other through the warp balancer or the core layer therebetween. The first wiring structure is disposed over the top build-up layer through connecting joints superimposed over the warp balancer. By the high modulus of the warp balancer, local thermo-mechanical stress can be counterbalanced to suppress warping and bending of the first and second wiring structures. Furthermore, mounting the first wiring structure over the second wiring structure can provide staged fan-out routing for the chip to improve routing efficiency and production yield.

Description

technical field [0001] The invention relates to a semiconductor assembly, especially a semiconductor assembly with a double wiring structure and a warped balance piece. Background technique [0002] High-performance microprocessors and ASICs require more advanced packaging technologies, such as flip-chip assembly, to meet various performance requirements. However, the routing density of existing laminated substrates is generally low, so there is not enough interconnection capability for chips with high I / O density. Coreless substrates made by a semi-additive process can meet the demand. However, other features such as mechanical integrity and reliability have not been addressed (see US Pat. Nos. 8,227,703 and 8,860,205). This is because the flip-chip assembly tends to warp after the chip is mounted on the substrate (e.g. figure 1 shown). The warpage caused by the mismatch of the coefficient of thermal expansion (CTE) may lead to disconnection between the semiconductor ch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/60
CPCH01L23/528H01L24/10H01L2224/10
Inventor 林文强王家忠
Owner BRIDGE SEMICON