Semiconductor structure and method of forming the same

Abstract

An embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a gate dielectric layer surrounding a groove in the substrate, the extending direction of the groove is parallel to the surface of the substrate, and the source region and the drain region are located in the groove The opposite sides of the top; the first grid includes a first work function layer and a first conductive layer, the first work function layer covers the bottom surface of the groove and part of the side walls, and the first conductive layer covers the surface of the first work function layer; Two gates, including a second work function layer and a second conductive layer, the second gate is stacked on the first gate and the top surface is lower than the substrate surface, the second work function layer covers the sidewall of the groove part, and the second conductive layer The layers are filled in the area surrounded by the second work function layer, and in the direction perpendicular to the substrate surface, the resistance of the second conductive layer per unit thickness is smaller than the resistance of the first conductive layer per unit thickness. The embodiments of the present invention are beneficial to reduce the leakage current of the semiconductor structure.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background technique [0002] When the electric field in the gate-drain overlap region is strong, the electrons near the interface of the overlap region undergo band-band tunneling between the valence band and the conduction band to form a current, which is generally called gate-induced drain leakage current ( gate-induce drain leakage, GIDL). [0003] The magnitude of the GIDL current is related to the thickness of the gate dielectric layer near the drain, the larger the thickness, the smaller the GIDL current. Therefore, in order to solve the GIDL current problem, the existing method usually uses a thicker gate dielectric layer in the MOS transistor. However, a thicker gate dielectric layer will make the control ability of the gate to the channel worse, and the threshold voltage will increase. ...

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Problems solved by technology

Therefore, in order to solve the GIDL current problem, the existing method usually uses a thicker gate dielectric layer in the MOS transistor. However, a thicker gate dielectric layer will make the control ability of the gate to the channel worse, and the threshold voltage will increase. In turn, the MOS transistor requires a higher driving voltage

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