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Low-power-consumption state control circuit

A state-controlled, low-power technology, applied in the field of low-power state control circuits, can solve problems such as difficult design, limited power consumption, and inability to control AON modules

Active Publication Date: 2021-06-29
SHANGHAI WU QI MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1. The current general state machine can only control the functional modules in the power management chip (PMU) except the always-on domain module (Alwayson Domain, referred to as AON module), and there is no way to control the AON module that is always on, so The power consumption that can be reduced is limited
[0005] 2. Using multiple state machines to control the working state, the state machine not only needs to consider how to enter each working mode correctly, but also needs to consider how to recover from the working state smoothly, the design is very difficult

Method used

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Examples

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Effect test

Embodiment 1

[0046] The low power consumption state control circuit includes a reset generation module, a first reset signal control module, a first signal generation module, a second reset signal control module and a second signal generation module, wherein:

[0047] The reset generation module is used to generate a reset signal according to the input key reset signal and the output signal of the power-on reset / power-down detection module.

[0048] The first reset signal control module is used for generating a first reset control signal according to the generated reset signal and the sleep end signal inside the power management chip.

[0049] The first signal generation module is used to simultaneously generate the first reset control signal and the first switch control signal for controlling the first voltage domain switch to control the function modules in the power management chip except the AON module to be powered off and The first power-down signal and the first isolation signal in th...

Embodiment 2

[0076] The difference with Embodiment 1 is that: if Figure 5 As shown, the first reset signal control module is further configured to generate the first reset signal according to the first isolation signal fed back by the first signal generation module and the input sleep end signal inside the power management chip.

[0077] The first reset signal control module includes a No. 3 NOR gate and a No. 4 NOR gate connected in sequence. One input terminal PMU_HIBER_RST_N_HV of the No. 3 NOR gate is used to input the dormancy end signal, and the other input terminal PMU_ISO_HV is used to input the first For isolation signals, the output terminal RST_PMU_LV of the fourth NOT gate outputs a PMU reset signal. In this embodiment, the first reset signal is active at low level, that is, when the first reset signal is at low level, the reset of the power management chip is triggered.

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Abstract

The invention relates to the technical field of semiconductor integrated circuits, and particularly discloses a low-power-consumption state control circuit. The circuit comprises a reset generation module used for generating a reset signal, a first reset signal control module used for generating a first reset control signal according to the input reset signal and a sleep ending signal in a power management chip, a first signal generation module used for simultaneously generating a first power-down signal and a first isolation signal according to the generated first reset control signal and a first switch control signal, a second reset signal control module used for generating a second reset control signal according to the generated reset signal, and a second generation module used for simultaneously generating a second power-down signal and a second isolation signal according to the generated second reset control signal and a second switch control signal. According to the technical scheme, when the working state of the power management chip is switched, a power supply normally open domain module can be controlled, and the power consumption of terminal equipment in the standby state is further reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a low power consumption state control circuit. Background technique [0002] With the widespread popularity of IoT devices, wireless terminal nodes widely collect various physical information and transmit data through smartphones or other network nodes. At the same time, the energy obtained by devices from batteries or external environments (such as solar energy) is very limited. , people have more and more stringent requirements on the power consumption of power management chips and systems. In most application scenarios, the time in sleep mode accounts for the highest proportion of the system, and the detection and calculation time is relatively small, such as figure 1 As shown, the power consumption in the sleep mode directly determines the life cycle of the device, and the current of the power management chip in the sleep mode is mainly divided into...

Claims

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Application Information

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IPC IPC(8): H03K17/22
CPCH03K17/22
Inventor 邱东
Owner SHANGHAI WU QI MICROELECTRONICS CO LTD