Self-aligned field effect transistor and preparation method thereof
A field-effect transistor and self-alignment technology, which is applied in transistors, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of increasing difficulty in lithography alignment process, achieve the effect of reducing alignment difficulty and optimizing performance
Pending Publication Date: 2021-08-24
上海芯导电子科技股份有限公司
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Problems solved by technology
[0015] The present invention provides a self-aligned field-effect transistor and its preparation method, aiming to solve the technical problem of increased difficulty in photolithography alignment process in the prior art when the size of SGT devices is further reduced
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[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0060] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.
[0061] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.
[0062] see Figure 2A-2I , image 3 and Figure 4 , the present invention provides a method for preparing a s...
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The invention provides a self-aligned field effect transistor and a preparation method thereof, and the method comprises the steps: sequentially forming a second oxide layer and a second dielectric layer on the surface of a silicon-based epitaxial layer and the surface of grid polycrystalline silicon, forming the second dielectric layer with side walls in the side wall regions of the two sides of the grid polycrystalline silicon, etching the second dielectric layer, reserving the second dielectric layer with the side walls, forming self-alignment of the contact hole by the second dielectric layer on the side wall, and etching the second oxide layer and the silicon-based epitaxial layer to form the contact hole. According to the technical scheme, the active region contact hole can be formed in the form of the side wall dielectric layer instead of a photoetching alignment mode, so that when the size of the device is further reduced, the alignment difficulty is reduced, and the performance of the device is optimized.
Description
technical field [0001] The invention relates to the technical field of transistor preparation, in particular to a self-aligned field effect transistor and a preparation method thereof. Background technique [0002] With the continuous shrinking of the size of power devices, the requirements of silicon-based MOSFETs for various individual processes are also increasing. How to ensure the stable mass production of the process under the smallest possible device structure is the key to the current mainstream MOS device manufacturing process. a challenge. [0003] Such as Figures 1A-1F , such as the manufacturing process of the prior art SGT mainly includes the following steps: [0004] Step A1, growing an oxide layer on the silicon-based epitaxial layer 1' as a barrier layer 2'; [0005] Step A2, covering the upper surface of the barrier layer with photoresist 3', developing and etching the barrier layer 2'; [0006] Step A3, removing the photoresist 3', etching the silicon-b...
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IPC IPC(8): H01L21/768H01L23/528H01L21/336H01L29/423H01L29/78H01L21/8234H01L27/088
CPCH01L21/76897H01L23/528H01L29/66477H01L29/78H01L29/42356H01L21/823475H01L27/088
Inventor 陈敏孙春明戴维符志岗欧新华袁琼朱同祥邱星福刘宗金
Owner 上海芯导电子科技股份有限公司