Chip circuit function verification system, method, equipment and storage medium

Abstract

The embodiment of the invention discloses a chip circuit function verification system, a method, equipment and a storage medium. The system comprises an excitation generation module, an execution module, a to-be-tested circuit, a reference model and a tester, the excitation generation module obtains a chip software simulation result, generates target verification excitation and inputs the target verification excitation to the execution module and the reference model; the execution module performs parameter configuration on the to-be-tested circuit according to the target verification excitation, generates a target excitation signal and inputs the target excitation signal to the to-be-tested circuit; the to-be-tested circuit generates a test output result according to the parameter configuration result and the target excitation signal; the reference model generates a reference output result according to the target verification excitation simulation; and the tester matches the test output result with the reference output result to obtain a function verification result of the circuit to be tested. According to the system of the invention, the time efficiency, the resource utilization rate and the accuracy of chip circuit function verification can be improved, and the realization of large-scale application scene verification is promoted.

Description

technical field [0001] The embodiments of the present invention relate to the field of chip technology, and in particular to a chip circuit function verification system, method, device and storage medium. Background technique [0002] In chip design, functional verification of chip integrated circuits in software application scenarios can test the core functions of chips in the early stage of circuit development, which is an essential link to ensure the success of chip design. With the emergence and development of ultra-large-scale chips such as 5G and artificial intelligence, the testing scale of chips in software application scenarios is becoming larger and more complex. [0003] figure 1 It is a schematic flow chart of a chip circuit function verification method in the prior art, figure 2 It is a schematic diagram of resources required for each stage of chip circuit function verification in the prior art, wherein the dotted box corresponds to the non-hardware circuit v...

AI Technical Summary

Problems solved by technology

[0004] However, the method provided in the above-mentioned prior art has the following defects: First, the verification work cannot be carried out before the specification of the application scenario is completed, resulting in insufficient mobilization of the human resources of the verification personnel

Secondly, verifiers need to collect and understand scenario information and manually write verification incentives based on the scenario information, resulting in a l...

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