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Error amplifier circuit with dynamic zero compensation

A technology of error amplifier and zero point compensation, which is applied in the field of analog circuit power management, can solve problems such as oscillation, achieve the effect of reduced phase margin attenuation, small bias current, and dynamic adjustment

Active Publication Date: 2021-09-03
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that the pole at the output node of the error amplifier is small and the output capacitance of the LDO varies in a large range under low quiescent current, and the output pole of the LDO varies in a wide range, causing the problem of oscillation

Method used

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  • Error amplifier circuit with dynamic zero compensation
  • Error amplifier circuit with dynamic zero compensation
  • Error amplifier circuit with dynamic zero compensation

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Embodiment Construction

[0016] Below in conjunction with accompanying drawing, technical solution of the present invention is described in detail:

[0017] The specific structural diagram of an error amplifier with dynamic zero point compensation proposed by the present invention is as follows figure 1 shown. It consists of three parts, namely bias circuit, error amplifier, and dynamic zero point compensation circuit. The bias circuit provides bias current for the differential amplifier; the differential amplifier can amplify the difference between the feedback voltage and the reference voltage, generate an error amplification signal to change the conduction degree of the power tube in the LDO, and keep the output voltage of the LDO constant; compensation The circuit is a pole-zero tracking compensation network that reduces the degradation of the phase margin at the output node of the error amplifier to enhance the overall loop stability of the LDO.

[0018] Specifically, the bias circuit includes:...

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Abstract

The invention belongs to the technical field of analog circuit power management, and particularly relates to an error amplifier circuit with dynamic zero compensation. The invention aims to solve the problem that oscillation is caused by a wide change range of an output pole of an LDO when the pole at an output node of an error amplifier under low quiescent current is small and the change range of output capacitance of the LDO is large. Four pairs of zero-pole pairs with fixed relative positions are designed at an output node of the error amplifier, so that the error amplifier is ensured to have high low-frequency gain, low intermediate-frequency gain is realized under low phase shift, a gain amplitude platform period can be reduced under the condition that limited phase attenuation is ensured, high loop gain can be realized at the same time, and the loop stability is high. In addition, by means of the dynamic resistor, the zero pole position of the error amplifier can change along with load conditions, and therefore the application range of the error amplifier is widened.

Description

technical field [0001] The invention belongs to the technical field of analog circuit power management, and in particular relates to an error amplifier circuit with dynamic zero point compensation. Background technique [0002] In recent years, concepts such as new energy, autonomous driving, and smart transportation have continued to develop, and a large number of electronic systems have assumed different roles in automobiles. Power management chips are the heart of energy conversion for electronic systems. The increasing number of on-board electronic devices and complex usage scenarios have put forward more stringent standards for power management chips and brought strong market demand. LDO is a common type of power management chip. Compared with other types of power management chips, it has the advantages of low output voltage ripple, low quiescent current and high loop bandwidth. Therefore, for the reliability, low power consumption and fast transient response requireme...

Claims

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Application Information

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IPC IPC(8): G05F1/56
CPCG05F1/56
Inventor 周泽坤娄建理王世杰王卓张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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