Main-grid-free heterojunction solar cell and prepared imbricated assembly thereof
A solar cell and heterojunction technology, applied in electrical components, circuits, photovoltaic power generation, etc., can solve the problems of high manufacturing cost, large consumption, and high cost of manufacturing equipment, and achieve the goal of reducing silver paste consumption and manufacturing cost Effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0017] In this embodiment, a 166mm N-type silicon wafer is used as a substrate. First, the N-type silicon wafer is cleaned and textured, and finally the intrinsic layer and the doped layer are uniformly vacuum-deposited on both sides of the N-type silicon wafer by PECVD technology, and then Continue to deposit a transparent conductive passivation layer (TCO) on the surface of the doped layer. Finally, a screen printing machine was used to print 110 fine grids evenly distributed on the front surface of the cell, with a width of 35um and an interval of 1.5mm between the grid lines. 150 evenly distributed fine grids are printed on the back of the cell, the width of the thin grids is 30um, and the distance between the grid lines is 1.1mm. After the busbar-free heterojunction solar cell is prepared, the cell is cut according to the module layout design. In this example, the 166mm cell is vertically divided into 6 equal parts along the vertical thin grid line, and the edge of each s...
Embodiment 2
[0019] In this embodiment, a 188mm N-type silicon wafer is used as a substrate. First, the N-type silicon wafer is cleaned and textured, and finally the intrinsic layer and the doped layer are uniformly vacuum-deposited on both sides of the N-type silicon wafer by PECVD technology, and then Continue to deposit a transparent conductive passivation layer (TCO) on the surface of the doped layer. Finally, a screen printing machine was used to print 130 fine grids evenly distributed on the front surface of the cell, with a width of 40um and an interval of 1.45mm between the grid lines. 170 evenly distributed fine grids are printed on the back of the battery sheet, the width of the thin grids is 30um, and the distance between the grid lines is 1.1mm. After the busbar-free heterojunction solar cell is prepared, the cell is cut according to the module layout design. In this embodiment, the 188mm cell is vertically cut into 7 equal parts along the direction of the vertical thin grid li...
Embodiment 3
[0021] In this embodiment, a 210mm N-type silicon wafer is used as a substrate. First, the N-type silicon wafer is cleaned and textured, and finally the intrinsic layer and the doped layer are uniformly vacuum-deposited on both sides of the N-type silicon wafer by PECVD technology, and then Continue to deposit a transparent conductive passivation layer (TCO) on the surface of the doped layer. Finally, a screen printing machine was used to print 180 fine grids evenly distributed on the front surface of the battery sheet, the width of the thin grids was 35um, and the distance between the grid lines was 1.17mm. 210 evenly distributed fine grids are printed on the back of the cell, the width of the thin grids is 30um, and the distance between the grid lines is 1.0mm. After the busbar-free heterojunction solar cells are prepared, the cells are cut according to the module layout design. In this embodiment, the 210mm cells are vertically cut into 9 equal parts along the direction of ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 

