Low-power-consumption sampling MOSFET power tube current circuit

Abstract

The invention discloses a low-power-consumption sampling MOSFET power tube current circuit which comprises an amplifier 1, a sampling tube M1, a power tube M0, an MOS tube M2, an MOS tube M3, a divider resistor R5 and a divider resistor R6, the divider resistor R5 and the divider resistor R6 are connected between the source electrode and the drain electrode of the power tube M0 in series, and the common connection point of the divider resistor R5 and the divider resistor R6 is connected with the positive input end of the amplifier 1; the MOS tube M3 and the MOS tube M2 share a grid electrode and a source electrode to form a current mirror, so that the original sampling current of the sampling tube M1 is redistributed, most of the sampling current can be returned and output to become output current, a small part of the sampling current flows into the ground through a sampling resistor, and the power consumption caused by the part of the current is reduced. The purpose of reducing sampling power consumption can be achieved by adjusting the proportion of divider resistors and the proportion of current mirrors of the MOS tube M3 and the MOS tube M2; and under the condition that the area proportion of the power tube to the sampling tube is small, for example, the MOSFET power tube is designed by adopting a separation device process, the structure is most suitable for being adopted.

Description

technical field [0001] The invention relates to electronic components, semiconductors and integrated circuits, in particular to a circuit for sampling the current of a MOSFET power tube with low power consumption. Background technique [0002] In the design of DC / DC converters, no matter which control method is used, the current sampling of the MOSFET power tube is essential. For example, in the valley current and peak current modes, it is necessary to sample the current of the power tube in each cycle. Combined with the current of the upper power tube, combined with the corresponding slope compensation, a current ramp is formed. The current ramp intersects with the output of the transconductance amplifier to generate a PWM signal to control the switch of the power tube. The slope of the current ramp needs to be precisely controlled. Within the set range, the stability of the control loop can be guaranteed, for example: in the peak current mode, the rising slope (m) of slope...

AI Technical Summary

Problems solved by technology

[0016] The sampling current is determined by V IN , through the sampling tube M 1 , MOS tube M 2 and the sampling resistor R 4 , all the way to the ground, the power consumption required for sampling is not only the sampling tube M 1 The power consumption, but the consumption of the sampling current in the entire path, if the power tube M 0 Using integrated circuit process design, the sampling tube M 1 The size has great flexibility, usually tens of ohms to several thousand ohms is easy to achieve, therefore, according to the requirements of power consumption, a large sampling ratio can be freely selected to obtain a small sampling current and reduce sampling power consumption , for example: power tube M 0 The on-resistance is 100mΩ, when N=10000, M 1 The on-resistance is 1000Ω at V IN =5V, I OUT = 1A, M 0 The power consumed is 100mW, and the extra power consumption caused by sampling is 0.5mW, which is 0.5%. However, the power tube M designed with integrated circuit technology 0 The structure is complex, for example: 20V withstand voltage power LDMOS (Laterally Double-Diffused MOSFET) under the current 0.18um process requires 18 layers of photomasks to complete the production. Today, for better performance and more competitive costs, the power tube M 0 The process design of separate semiconductor devices is often used, for example: the same 20V withstand voltage power tube M 0 , only 5 layers of photomasks are required under the separation device process, the cost advantage is obvious, the sampling tube M 1 required with power tube M 0 Using the same process can ensure the matching of various electrical properties. Therefore, the sampling tube M 1 and power tube M 0 On the same wafer (Wafer), the control circuit must be designed with integrated circuit technology, and another wafer is needed. When packaging, it is inevitable to seal the bare chips (Die) from the two wafers together. ,like figure 2 As shown, the power tube M 0 and sampling tube M 1 The sources of the wires are respectively connected to the control circuit by wire bonding. Bond Pad is required for wire bonding, and its size is proportional to the wire diameter of the wire. For example, a copper wire with a wire diameter of 1.2mil (=30.48um) needs 90um x 90um pad

The size of the pad cannot be larger than the size of the source of the MOSFET, because in this case there will be a large free area under the pad, which will reduce the sample density of the source (Pattern Density) and affect its electrical characteristics, that is, Sampling tube M 1 The minimum size is limited by the size of the pad, for example: image 3 The 20V withstand voltage power tube M shown in 0 The equivalent resistance is 15mΩ, the power tube M 0 with sampling tube M 1 The area ratio is approximately 64, the V IN =5V, I OUT =1A, power tube M 0 The power consumed is 15mW, and the extra power consumption caused by sampling is 78mW, which is higher than the power tube M 0 The consumption is still large!

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