Semiconductor structure and forming method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a forming method thereof. The method comprises the following steps that: a semiconductor substrate is provided, wherein the surface of the semiconductor substrate is provided with a plurality of active regions and shallow trench isolation regions which are arranged along a first direction; the active regions and the shallow trench isolation regions are etched along the direction vertical to the first direction to form a first concave hole and a second concave hole; the surfaces of the first concave hole and the second concave hole are covered with an adhesion layer and a metal layer; and secondary etching is performed on the metal layer and the adhesion layer along the direction perpendicular to the first direction to form a contact hole, and the depth of the adhesion layer is defined in the contact hole as H2. According to the semiconductor structure and the forming method thereof of the invention, the effective distance between the grid ends of embedded word lines adjacent to the active regions is increased through the secondary etching, so that the additional electric field between the adjacent embedded word lines is weakened, the grid induction drain leakage effect is improved, and the refreshing efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] DRAM is a semiconductor memory widely used in multi-computer systems. With the continuous shrinking of the feature size of semiconductor integrated circuit devices, the dynamic random access memory is also continuously developing towards a high density. Therefore, it poses a more severe challenge to the semiconductor manufacturing technology. [0003] In the existing semiconductor technology field, due to the design layout of the structure, the buried word line (WL) will pass through the active area (AA) and the shallow trench isolation region (STI) at the same time, and the buried of the shallow trench isolation region When the word line is in operation, it will be coupled with the active area of ​​the parallel buried word line, so that there will be an extra strong electric field from ...

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Problems solved by technology

With the continuous shrinking of the feature size of semiconductor integrated circuit devices, dynamic random access memory is also developing towards high integration density. Therefore, it poses more severe challenges to semiconductor manufacturing technology.

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