Formation method of semiconductor structure

Abstract

The invention discloses a formation method of a semiconductor structure, which comprises the steps of forming a plurality of first openings in a dielectric layer, wherein the bottom of each first opening exposes the top surface of a first source-drain doped region; forming a plurality of second openings in the dielectric layer, wherein the bottom of each second opening exposes part of the surface of the top of one first gate structure; and forming a plurality of third openings in the dielectric layer, wherein the bottom of each third opening is higher than the top surface of the first gate layer, and the third openings are communicated with the first openings and the second openings respectively. According to the method, mutual influence between different manufacturing processes can be reduced, so that the performance of the formed semiconductor structure is relatively good.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. Transistors, as the most basic semiconductor devices, are being widely used at present. The control ability of traditional planar devices on channel current is weakened, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the fin field effect transistor includes : the fin and the isolation layer located on the surface o...

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Problems solved by technology

[0004] However, when the source-drain doped region and the gate structure are electrically connected to the peripheral circuit through a common plug, the performance of the existing semiconductor structure is poor.

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