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Longitudinal BCD device capable of inhibiting parasitism and preparation method thereof

A device and vertical technology, which is applied in the field of vertical BCD devices and its preparation, can solve the problems of large area occupied by DMOSFET drain area, large on-resistance, and poor compatibility of VDMOSFET, so as to improve chip utilization, reduce on-resistance, The effect of reducing chip area

Active Publication Date: 2021-11-23
SHAANXI REACTOR MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problems of large occupied area of ​​the drain region of the existing DMOSFET, large on-resistance and poor compatibility of VDMOSFET, and provide a vertical BCD device capable of suppressing parasitic and its preparation method

Method used

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  • Longitudinal BCD device capable of inhibiting parasitism and preparation method thereof
  • Longitudinal BCD device capable of inhibiting parasitism and preparation method thereof
  • Longitudinal BCD device capable of inhibiting parasitism and preparation method thereof

Examples

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Effect test

Embodiment 1

[0059] figure 1 Shown is a schematic structural diagram of a vertical BCD integrated device. Taking an N-type planar VDMOSFET device as an example, it can also be a VDMOSFET device with a trench or super junction structure. The vertical BCD device can reduce the on-resistance and reduce the chip area. , However, it also has a defect at the same time, the voltage added to the drain of the VDMOSFET will also affect the CMOS device in the BCD device. Therefore, a P-well needs to be added to isolate the CMOS devices. Since the deep P-well HVPW is used alone to realize the well, the well is deep and requires high process capability and precision. Due to the limitation of machine capacity, the depth of HVPW can be reduced by making P-type buried layer PBL, and the corresponding process is easier to realize. In addition, the concentration of PBL in the buried layer can be adjusted, and increasing the concentration of PBL can effectively inhibit the conduction of the parasitic tube ...

Embodiment 2

[0084] Figure 11 Vertical BCD devices shown in the figure 1 On the basis of the structure, a layer of HVNW deep N-type well is added. The main function is to prevent the reverse breakdown of the diode formed between the N-Well of PMOS and HVPW in CMOS, which will affect the normal operation of PMOS. Since N-Well is mainly used to adjust the channel parameters of PMOS, at the same time, it is difficult to take into account the reverse withstand voltage of HVPW. Therefore, it is necessary to add a layer of HVNW deep N well to adjust the reverse of the diode formed between HVPW and HVPW. The reverse withstand voltage must be greater than the breakdown withstand voltage of the PMOS. In the figure, VC2 is the lead-out end of the HVNW.

[0085] The specific structure of the vertical BCD device in this embodiment is as follows, including:

[0086] N-type substrate,

[0087] The first N-type epitaxial layer formed on the upper surface of the N-type substrate, the first N-type epit...

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Abstract

The invention provides a longitudinal BCD device capable of inhibiting parasitism and a preparation method thereof. The problems that a drain electrode region of an existing DMOSFET is large in occupied area and large in on resistance, and a VDMOSFET is poor in compatibility are mainly solved. According to the longitudinal BCD device, a deep P well HVPW and a P-type buried layer PBL are added in a CMOS device region, so that diodes are formed among the HVPW, the PBL and an N-type epitaxial layer N-EPI, when a VDMOSFET device works normally, the diodes formed among the N-EPI, the HVPW and the PBL are cut off reversely, reverse breakdown cannot occur, the influence on the CMOS device in the BCD device when voltage is applied to a drain electrode of the VDMOSFET is avoided, and meanwhile, the PBL buried layer serves as a base region of a parasitic tube NPN transistor in the BCD device, and conduction of the parasitic tube NPN transistor can be restrained by adjusting the concentration.

Description

technical field [0001] The invention relates to the technical field of monolithic integration technology, in particular to a vertical BCD device capable of suppressing parasitic and a preparation method thereof. Background technique [0002] BCD (BIPOLAR-CMOS-DMOS) integration process is a monolithic integration process technology that combines Bipolar (bipolar transistor), CMOS (complementary metal oxide semiconductor field effect transistor) and DMOSFET (double diffused metal oxide semiconductor field effect transistor) ) devices are fabricated simultaneously on the same chip. It combines the advantages of each device itself, so that it has good performance when it is discrete. The integrated BCD process can greatly reduce power consumption, improve system performance, save costs, and have better reliability. [0003] There are two main types of DMOSFET: lateral double diffused metal oxide semiconductor field effect transistor LDMOSFET and vertical double diffused metal ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L21/8249H01L29/06H01L27/06
CPCH01L29/7802H01L27/0623H01L21/8249H01L29/0619H01L29/66712
Inventor 刘雯娇杨世红
Owner SHAANXI REACTOR MICROELECTRONICS
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