Packaging structure, circuit board assembly and electronic equipment

A packaging structure and packaging cover technology, which is applied to printed circuit components, circuits, printed circuits, etc., can solve problems such as poor welding of chips and circuit boards, increased internal stress of the package, and increased power consumption of the chip, so as to improve production capacity and stability performance, reducing warpage, and reducing package weight

Active Publication Date: 2022-01-28
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the size of the package increases, the warpage of the package will also increase. The warpage of the package will not only increase the internal stress of the package, but also lead to poor soldering between the chip and the circuit board, resulting in problems such as soldering and soldering.
The increase in power consumption of the chip causes the chip to generate and emit more heat, which puts forward higher requirements for the heat dissipation of the chip package.

Method used

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  • Packaging structure, circuit board assembly and electronic equipment
  • Packaging structure, circuit board assembly and electronic equipment
  • Packaging structure, circuit board assembly and electronic equipment

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] See Figure 3A , Figure 3B and Figure 3C , Figure 3A , Figure 3B and Figure 3C A structural diagram of the package structure 1 provided by one embodiment of the present invention is shown. in, Figure 3A A schematic view of a top surface structure of the package structure 1, Figure 3B for Figure 3A Schematic diagram of the profile structure in I, Figure 3C for Figure 3B Schematic diagram of the cross-sectional structure of IIII. exist Figure 3A , Figure 3B and Figure 3C In the illustrated embodiment, the package structure 1 includes a substrate 10, an electronic component 20, and a package cover 50. Wherein, the substrate 10 has a relatively disposed first surface and a second surface, the electronic component 20 connected to the first surface of the substrate 10, the package cover 50 including a top cover 510, a first support portion 521 and the second support portion 522, the top cover 510 is coupled to the first surface of the substrate 10 by the first support portion 521 ...

Embodiment 2

[0050] See Figure 4A , Figure 4b and Figure 4C , Figure 4A , Figure 4b and Figure 4C Shows a schematic structural diagram of the present invention to provide a package structure embodiment 1 of the embodiment. in, Figure 4A Is a schematic top view of the structure of package 1, Figure 4b for Figure 4A The cross-sectional structure of schematic Ⅲ, Figure 4C for Figure 4b A schematic cross-sectional structure at Ⅳ. exist Figure 4A-Figure 4C In the embodiment shown, package 1 comprises: a substrate 10, electronic components 20 and the package lid 50. Wherein, the substrate 10 having a first surface and a second surface oppositely disposed, the electronic component 20 is connected to the first surface of the substrate 10, the package lid 50 includes a top cap 510, a first support portion 521, the second supporting portion 522 and third support portions 523, 510 of the cap portion 521 by a first support, a second support portion 522 and the third supporting portion 523 is connected to ...

Embodiment 3

[0056] Please refer to Figure 5 , Figure 5 A schematic transverse cross-sectional structural diagram of a package 1 is illustrated another embodiment of the present invention. What needs to be explained, Figure 5 A top structure and a longitudinal cross-sectional structure of a package structure may correspond to the embodiment shown with reference to Figure 3A , Figure 3B The structure of the illustrated embodiment, it is omitted here. Figure 5 The package structure shown in the embodiment 1 comprises: a substrate 10, electronic components 20 and the package lid 50. Wherein, the substrate 10 having a first surface and a second surface oppositely disposed, the electronic component 20 is connected to the first surface of the substrate 10, the package lid 50 includes a top cap 510, a first support portion 521 and the second supporting portion 522, the cap 510 by the first supporting portion 521 and the second support portion 522 is connected to the first surface of the substrate 10,...

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PUM

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Abstract

The invention provides a packaging structure, a circuit board assembly and electronic equipment. The packaging structure comprises a substrate, an electronic component and a packaging cover body, wherein the substrate has a first surface and a second surface which are oppositely arranged, the electronic component is connected with the first surface of the substrate, the packaging cover body comprises a top cover, a first supporting part and a second supporting part, and the top cover is connected to the first surface of the substrate through the first supporting part and the second supporting part, so that the coverage area of the top cover on the substrate can be maximized, and the warping of the substrate is controlled; a first cavity is defined between the first supporting part and the second supporting part, so that other devices such as a capacitor and the like can be conveniently mounted on the substrate, and the packaging weight can be reduced; and the top cover has an opening at a position corresponding to the electronic component, at least part of the electronic component is exposed from the opening, and the electronic component can be in direct contact with air or a radiator, so that the heat dissipation effect of the packaging structure is ensured.

Description

Technical field [0001] The present invention relates to the field of semiconductor packaging, and in particular, to a package structure, a circuit board assembly, and an electronic device. Background technique [0002] With the rapid development of science and technology, the chip requirements are getting higher and higher, and the package size and chip power consumption are rapidly increased. As the package size increases, the package warpage increases. The package warpage will not only increase the internal stress of the package, but also cause problems such as even tin, vented welding, etc. The chip power consumption increases the chip to generate and distribute more heat, and puts higher demand for chip package heat dissipation. Inventive content [0003] The embodiment of the present invention provides a package structure, a circuit board assembly, and an electronic device to effectively control the warpage of the package structure, and does not affect the heat dissipation ...

Claims

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Application Information

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IPC IPC(8): H01L23/04H01L23/31H01L23/367H05K1/02H05K1/18
CPCH01L23/04H01L23/3157H01L23/367H05K1/0271H05K1/181H05K1/0209
Inventor 陈时雨杨丹梅娜孙拓北
Owner SANECHIPS TECH CO LTD
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