Interface circuit, data transmission circuit and memory

Abstract

The embodiment of the invention provides an interface circuit, a data transmission circuit and a memory, the interface circuit comprises a clock bonding pad, data bonding pads and an input buffer circuit, the clock bonding pad and the data bonding pads are arranged in a first row, M data bonding pads are arranged on two sides of the clock bonding pad, half of the M data bonding pads are arranged on each side, the M input buffer circuits are arranged in the second row, an axis perpendicular to the first row is formed by taking the data bonding pad as a reference, the M input buffer circuits are arranged on the two sides of the axis, half of the M input buffer circuits are arranged on each side, and the distance between each input buffer circuit and the axis is smaller than the distance between the data bonding pad corresponding to the input buffer circuit and the axis. According to the embodiment of the invention, the length of the clock path corresponding to each input buffer circuit is shortened, the time sequence violation is reduced, and the matching degree of the clock path corresponding to each input buffer circuit and the input data path is improved.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of semiconductors, and in particular to an interface circuit, a data transmission circuit and a memory. Background technique [0002] Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, and is composed of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage. [0003] DRAM can be divided into Double Data Rate (DDR) DRAM, GDDR (Graphics Double Data Rate) DRAM, and Low Power Double...

AI Technical Summary

Problems solved by technology

[0004] However, current DRAM performance still needs to be improved

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