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Semiconductor structure and forming method thereof

A technology of semiconductor and gate structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc. performance effect

Pending Publication Date: 2022-03-04
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of semiconductor structures formed in the prior art still needs to be improved

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] It should be noted that "surface", "upper", for describing the relative positional relationship of the space, is not limited to whether or not it is directly in contact.

[0030] First, the reason for the performance of existing semiconductor structures is detailed in connection with the accompanying drawings. Figure 1 to 5 It is a schematic structural diagram of the formation method of existing semiconductor structures.

[0031] Please refer to figure 1 Provide substrate 100, the substrate 100 comprising a first region I and a second zone II having a gate structure 110 and a first dielectric layer 120 on the first zone I and a second zone II, the gate structure 110. The substrate 100 on both sides has a source leak doping region 111 having a source leakage plug 130 having a source leakage plug 130, the first dielectric layer 120 located at the gate structure 110 and a source leak-doped doping. District 111 and the surface of the source leakage plug 130.

[0032] Please ref...

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PUM

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Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: forming a second dielectric layer on the surfaces of a first dielectric layer, a gate structure and a source-drain plug; forming a connecting plug in the second dielectric layer, wherein the connecting plug is located on the top surfaces of the adjacent gate structure and the source-drain plug; forming a third dielectric layer on the surfaces of the second dielectric layer and the connecting plug; a first plug is formed in the third dielectric layer, the top surface of the first plug is higher than the top surface of the connecting plug, and the first plug is electrically connected with the connecting plug. The connecting plugs are isolated through the third dielectric layer, the connecting plug needing to be externally connected is selected through the first plug, and due to the fact that the area occupied by the first plug is small, the follow-up wiring difficulty of the conducting layer can be reduced.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing techniques, and more particularly to a semiconductor structure and a method of forming thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technologies, people's requirements for integrated circuits become higher and higher. In order to improve integration, reduce cost, the key size of the component is constantly smaller, the circuit density inside the integrated circuit is increasing, which makes the wafer surface unable to provide sufficient area to make the required interconnect. [0003] The connection plug within the transistor structure includes a connection plug located on the gate structure surface for connecting the gate structure and an external circuit; and a connection plug located on the surface of the source leak-doped region for realizing the transistor source region or The drain area is connected to the external ci...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/768H01L29/417H01L29/423
CPCH01L21/76831H01L21/76879H01L21/76847H01L21/76816H01L23/5283H01L29/41725H01L29/42356
Inventor 赵炳贵
Owner SEMICON MFG INT (SHANGHAI) CORP