Nonvolatile SRAM unit based on hafnium-based ferroelectric capacitor

Abstract

The nonvolatile SRAM unit comprises a 6T SRAM and a nonvolatile storage module, the nonvolatile storage module comprises a fifth NMOS (N-channel metal oxide semiconductor) tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first hafnium-based ferroelectric capacitor and a second hafnium-based ferroelectric capacitor and is of a 4T2C structure, and in the nonvolatile storage module, the first hafnium-based ferroelectric capacitor is connected with the second hafnium-based ferroelectric capacitor. A pair of hafnium-based ferroelectric capacitors, namely a first hafnium-based ferroelectric capacitor and a second hafnium-based ferroelectric capacitor, is adopted as nonvolatile memory devices to form a complementary bilateral structure, data in a 6T SRAM (Static Random Access Memory) is stored in the first hafnium-based ferroelectric capacitor and the second hafnium-based ferroelectric capacitor before power failure, and then the circuit is completely turned off, so that the standby power consumption is saved, and the power consumption is reduced. A complementary bilateral structure formed by the first hafnium-based ferroelectric capacitor and the second hafnium-based ferroelectric capacitor can improve the data recovery rate and the reliability of resisting process change; the method has the advantages of being high in data recovery rate and good in reliability of resisting process changes.

Description

technical field [0001] The invention relates to a nonvolatile SRAM unit, in particular to a nonvolatile SRAM unit based on a hafnium-based ferroelectric capacitor. Background technique [0002] Non-volatile SRAM (NVSRAM) is formed by integrating CMOS SRAM with non-volatile memory (NVM) in one cell. NVSRAM generally has three working modes: normal SRAM mode, storage mode and recovery mode. In normal SRAM mode, NVSRAM works as a SRAM unit to complete the reading, writing and retention of data in CMOS SRAM; in storage mode, when NVSRAM is powered off, it stores the data in CMOS SRAM in NVM, and the data will not be lost after power off; In the recovery mode, the data stored in the NVM is restored to the CMOS SRAM when the NVSRAM is powered on. Compared with the method of using a non-volatile system composed of a centralized NVM core, NVSRAM realizes bit-to-bit, parallel data transmission, fast storage and recovery of data, and low power consumption. Document 1 (C Liu, Q Wang...

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Problems solved by technology

Document 1 (C Liu, Q Wang and J.Y Yang et al. IEEE International Conference on Solid-State & Integrated Circuit Technology, p.1-3 (2020). A NVSRAM with a 7T1C structure is disclosed. In this NVSRAM, 6 CMOS The device constitutes 6T SRAM, 1 CMOS and 1 hafnium-based ferroelectric capacitor constitute 1T1C fer

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