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GOI test circuit structure

A technology for testing circuits and connection holes, applied in the field of semiconductor testing, can solve the problems of TEM samples that cannot see the failure point, the breakdown position is not obvious, and the failure point is easy to miss, etc., achieving high practical value, strong realizability, and clarity The effect of positioning

Active Publication Date: 2022-04-12
NEXCHIP SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] For the failure point that can be seen directly in the salicide layer, when preparing the TEM sample by cutting the section, since there is no ruler that can be used for positioning, and because the breakdown position is not obvious, it is easy to miss the actual failure point, resulting in the preparation of the TEM sample. to failure point or no failure point

Method used

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  • GOI test circuit structure
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  • GOI test circuit structure

Examples

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Embodiment Construction

[0024] figure 1 It is a structural schematic diagram of a GOI test circuit structure. Such as figure 1 As shown, the current GOI test circuit structure includes a plurality of parallel strip-shaped AA regions 1 formed in the front surface of a substrate, and STI2 is arranged between adjacent AA regions 1, and sequentially on the substrate A gate oxide layer and a polysilicon gate 3 are formed, the gate oxide layer covers the AA region 1 and STI2, the polysilicon gate 3 covers the gate oxide layer, and at least a first Metal layer 4 , the first metal layer 4 includes a plurality of metal squares, all of which may be located above the STI 2 and above the AA region 1 .

[0025] It can be seen that since the hot spot above the AA area is blocked by the metal square, it is impossible to locate the hot spot when performing electrical testing and positioning from the back of the substrate. When preparing TEM samples by peeling off layers and cutting sections, because there is no ru...

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Abstract

The invention provides a GOI test circuit structure, which comprises a plurality of strip-shaped AA regions formed in a substrate and arranged in parallel, STIs are formed between adjacent AA regions, a gate oxide layer, a polycrystalline silicon grid electrode and a plurality of counting structures are sequentially formed on the substrate, all the counting structures are arranged in parallel, each counting structure is correspondingly arranged above one STI, and each counting structure is arranged above one STI. Each counting structure is arranged close to one AA area and is used for positioning the hot spots in the AA areas, so that clear positioning of the electric test hot spots can be realized, a hot spot positioning standard is provided for physical stripping and FIB section cutting to prepare TEM samples, the GOI test failure analysis efficiency and the success rate of target position section cutting are greatly improved, and the detection accuracy of the TEM samples is improved. In addition, the manufacturing process is high in realizability, and high practical value is achieved.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a circuit structure for GOI (Gate Oxide Integrity, gate oxide integrity) testing. Background technique [0002] GOI test is a reliability test to evaluate the quality of the gate oxide layer in MOS devices. For samples with abnormal GOI failure, GOI failure analysis is required to find out the root cause of GOI test failure and assist in process improvement. Due to the large area of ​​the GOI test circuit structure, the failure point is not obvious, so it is necessary to conduct an electrical test to locate the failure point (that is, the hot spot position), and then perform peeling for the hot spot position, and then peel the layer to the polysilicon gate. When finding the exact failure point, cut the section (that is, use the FIB section) to prepare the TEM sample, and obtain the composition of the abnormal substance at the GOI failure point through TEM observation and elem...

Claims

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Application Information

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IPC IPC(8): G01R31/26G01N23/04G01N23/20G01N1/28H01L23/544
Inventor 俞佩佩王丽雅胡明辉
Owner NEXCHIP SEMICON CO LTD