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A goi test circuit structure

A technology for testing circuits and connecting holes, which is applied in the field of semiconductor testing, can solve the problems that the breakdown position is not obvious, the failure point is easy to miss, and the failure point cannot be seen in TEM samples, etc., achieving high practical value, strong realizability, and clarity The effect of positioning

Active Publication Date: 2022-06-17
NEXCHIP SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] For the failure point that can be seen directly in the salicide layer, when preparing the TEM sample by cutting the section, since there is no ruler that can be used for positioning, and because the breakdown position is not obvious, it is easy to miss the actual failure point, resulting in the preparation of the TEM sample. to failure point or no failure point

Method used

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  • A goi test circuit structure
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  • A goi test circuit structure

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Embodiment Construction

[0024] figure 1 It is a structural schematic diagram of a GOI test circuit structure. like figure 1 As shown, the current GOI test circuit structure includes a plurality of elongated AA regions 1 arranged in parallel and formed in the front surface of a substrate, and STI2 is arranged between adjacent AA regions 1, and the substrates are arranged in sequence on the substrate. A gate oxide layer and a polysilicon gate 3 are formed, the gate oxide layer covers the AA region 1 and the STI2, the polysilicon gate 3 covers the gate oxide layer, and at least a first gate oxide layer is formed above the polysilicon gate 3 Metal layer 4 , the first metal layer 4 includes a plurality of metal squares, all of which may be located over STI 2 and over AA area 1 .

[0025] It can be seen that since the hot spot located above the AA area is blocked by the metal square, it is impossible to locate the hot spot during the electrical testing and positioning from the backside of the substrate. ...

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Abstract

The present invention provides a GOI test circuit structure, which includes a plurality of strip-shaped and parallel AA regions formed in a substrate, STI is formed between adjacent AA regions, and gate oxide layers are sequentially formed on the substrate , polysilicon gate and multiple counting structures, all counting structures are arranged in parallel, each counting structure is correspondingly arranged above one STI, each counting structure is arranged close to an AA area, and is used to locate hot spots in the AA area, which can realize Clear positioning of hot spots for electrical testing, and provide hot spot positioning standards for physical peeling and FIB section preparation of TEM samples, greatly improving the efficiency of GOI test failure analysis, and the success rate of hitting the target section can also be improved in the process. Realization is strong, and has very high practical value.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a circuit structure for GOI (Gate Oxide Integrity, gate oxide integrity) testing. Background technique [0002] GOI test is a reliability test to evaluate the quality of gate oxide layer in MOS devices. For samples with abnormal GOI failure, GOI failure analysis is required to find out the root cause of GOI test failure to assist process improvement. Due to the large area of ​​the GOI test circuit structure, the failure point is not obvious, which requires an electrical test to locate the failure point (that is, the hot spot position), and then peel off the layer for the hot spot position, and then strip the layer to the polysilicon gate. When the exact failure point is found, the TEM sample is prepared by cutting the cross-section (that is, using FIB to cut the cross-section), and the composition of abnormal substances at the GOI failure point is obtained through TEM observa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26G01N23/04G01N23/20G01N1/28H01L23/544
Inventor 俞佩佩王丽雅胡明辉
Owner NEXCHIP SEMICON CO LTD