Low-power-consumption rapid dynamic comparator

A dynamic comparator, low-power technology, applied in the field of microelectronics, can solve problems such as comparator power consumption offset delay, affecting ADC performance characteristics, etc., to achieve the effect of reducing dynamic power consumption and improving comparison accuracy

Pending Publication Date: 2022-04-12
CHONGQING UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In any case, traditional comparators have problems such as power consumption, of

Method used

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  • Low-power-consumption rapid dynamic comparator
  • Low-power-consumption rapid dynamic comparator
  • Low-power-consumption rapid dynamic comparator

Examples

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[0022] Example

[0023] A low-energy fast-moving dynamic comparator comprising: pre-amplifier 1, comparison circuit 2, and latch 3, wherein the signal output of the pre-amplifier 1 is terminated on the signal input of the comparison circuit 2, the comparison circuit. 2 The signal output of the latch 3; the pre-amplifier 1 pre-substates the input signal of the input terminal Vn and the input terminal VP and outputs a signal at the output VNN and the output VPP output signal. The comparison circuit 2 dynamically compares the signal of the output terminal VNN of the pre-amplifier 1, and provides an input signal for the latch 3, the latch 3 receives the output signal of the comparison circuit 2 and A latch is implemented under the action of the clock signal CLK, thereby implementing a low-cost fast-moving dynamic comparator.

[0024] As a preferred technical solution, such as figure 2 As shown, the pre-amplifier 1 includes: NMOS tube M1, NMOS tube M2, NMOS tube M3, PMOS tube M4, PMOS ...

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Abstract

The invention discloses a low-power-consumption rapid dynamic comparator, and belongs to the technical field of microelectronics. Comprising a pre-amplifier, a comparison circuit and a latch, the signal output end of the pre-amplifier is connected with the signal input end of the comparison circuit, and the signal output end of the comparison circuit is connected with the signal input end of the latch; a PMOS tube is adopted to form a body diode structure to reduce the dynamic power consumption of the circuit, the grid electrode of the body diode is connected with a bias voltage end, the voltage drop of the body diode is adjusted through the bias voltage, the speed of the comparator is adjusted, and the circuit delay is reduced; two back-to-back cross-coupled transistors are adopted as loads of the pre-amplifier, the gain of the pre-amplifier is improved, two output ends of the pre-amplifier are connected with transmission gates controlled by clock signals, and the problem that the speed of a comparator is affected by circuit charge imbalance is solved; the comparison circuit adopts two inverters which are in back-to-back cross coupling connection to form a positive feedback structure, so that the comparison precision is improved, and the system works in a stable state.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a fast dynamic comparator with low power consumption. Background technique [0002] Analog-to-digital converter (ADC), as an interface circuit connecting analog and digital signals, has become an important part of the system on chip (SoC). As an important part of ADC, the performance of comparator directly affects the performance of ADC, which in turn affects SoC performance characteristics. [0003] figure 1 It is a traditional comparator, mainly composed of NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9 and PMOS tube M10 . When the clock signal CLK=0 and CLK-N=1, the comparator is in the amplification stage. At this time, the tail current NMOS transistor M1 is in the conduction state, and the PMOS transistor M2 and the PMOS transistor M3 are input transistors and compare the in...

Claims

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Application Information

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IPC IPC(8): H03K5/24
Inventor 周前能朱江钰李红娟
Owner CHONGQING UNIV OF POSTS & TELECOMM
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