Preparation method of wafer-level reconfigurable Chiplet integrated structure

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly provides a preparation method of a wafer-level reconfigurable Chiplet integrated structure, and the method comprises the following steps: S1, preparing a reconfigurable topology network on a wafer, and covering the reconfigurable topology network with an insulating layer; s2, a groove is prepared in the wafer, and passivation is carried out; s3, putting the Chiplet into the groove, carrying out chemical mechanical polishing, and connecting the Chiplet with the reconfigurable topology network; s4, preparing a silicon through hole and a micro bump on the wafer, and thinning the silicon through hole and the micro bump; s5, stacking and bonding the multiple layers of wafers; and S6, carrying out scribing and packaging on the bonded multi-layer wafer. The wafer-level reconfigurable Chiplet integrated structure prepared by the method disclosed by the invention has a reconfigurable characteristic; the multilayer wafer stacking process can avoid the problem of poor stability caused by sub-module failure; the vertical stacking structure enables the area and length of horizontal wiring to be reduced, and the area overhead of the integrated structure is reduced; therefore, the integrated structure prepared by the method is relatively high in applicability and stability and relatively high in integration level.

Description

technical field [0001] The present application belongs to the technical field of semiconductor packaging, and in particular, relates to a method for preparing a wafer-level reconfigurable Chiplet integrated structure. Background technique [0002] Chiplet-based integration technology is to divide a large-scale monolithic integrated circuit into multiple sub-modules of different process types and line widths, that is, Chiplets are integrated in the same package through an adapter board. Since each chiplet can be fabricated using the optimal process node, the yield rate of the overall system can be greatly improved. It not only meets the needs of miniaturization of electronic systems, but also shortens the development cycle of new products by reusing existing Chiplets. [0003] However, the existing preparation methods of chiplet-based integrated structures still have certain defects. For example: the system configuration is fixed and cannot be reconfigured during the use ph...

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Problems solved by technology

[0004] The object of the present invention is to provide a method for preparing a wafer-level reconfigurable Chiplet integrated structure in view of the deficiencies in the above-mentioned prior art, so as to solve the problem of the integrated structure prepared by the method for preparing an integrated structure based on Chiplet in the prior art. Poor applicability and stability, and low integration

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