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Semiconductor structure and forming method thereof

A semiconductor and gate structure technology, applied in the field of semiconductor structures and their formation, can solve problems such as poor performance of semiconductor devices, and achieve the effects of reducing contact window resistance and sheet resistance, improving performance, and increasing cross-sectional size.

Pending Publication Date: 2022-05-06
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the contact window resistance and sheet resistance of the semiconductor device obtained through the above processing lead to poor performance of the semiconductor device

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0046] The currently formed devices still have poor performance. Now, the reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.

[0047] Please refer to Figure 1a-Figure 3c , Figure 1a to Figure 3c It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure. Among them, figure b in each group of figures is a schematic diagram of the structure obtained along the section line A-A' in figure a, figure c is a schematic diagram of the structure obtained along the section line BB' in figure a, and figure a is a schematic diagram of the structure obtained along the section line C in figure b Schematic diagram of the structure obtained by the section line of -C' or the section line along DD' in c.

[0048] Such as Figure 1a-Figure 1c As shown, a base is provided, and the base includes a substrate 110, a gate structure 12 located above the substrate 110, so...

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Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: carrying out the etching of a supporting layer after the processing of a gate structure, obtaining a remaining supporting layer, forming a second dielectric layer covering the remaining supporting layer, and forming a processing platform for forming a first groove, since the first dielectric layer and the second dielectric layer are made of the same material, when the first groove is formed, the first dielectric layer and the second dielectric layer above the source-drain doped region and the second dielectric layer above the residual supporting layer can be removed at the same time, so that the sectional dimension of partial section in the first groove can be increased, and the yield of the first groove is improved. And the sectional dimension of a part of section of the source-drain conductive plug formed in the first groove can be further increased, so that the resistance of the source-drain conductive plug is reduced while the electrical connection of the source-drain doped region is realized.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] During the processing of semiconductor devices, after ion implantation and doping, due to the high energy of the implanted ions, it is easy to cause lattice defects in the semiconductor structure. In order to eliminate some of the lattice defects, it is necessary to anneal the semiconductor structure. [0003] In the existing HKMG (high dielectric constant insulating layer + metal gate) processing technology, the polysilicon gate is generally formed first, and then the polysilicon gate structure is replaced by a high dielectric constant insulating layer + metal gate. However, during the annealing process, the gate spacer is prone to deformation, resulting in incomplete removal of the polysilicon. Therefore, in order to prevent deformation of the gate s...

Claims

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Application Information

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IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/823437H01L21/823475H01L27/088
Inventor 赵炳贵
Owner SEMICON MFG INT (SHANGHAI) CORP
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