Functional chip for 3D chip

Abstract

The embodiment of the invention provides a functional chip for a 3D chip. The functional chip comprises a substrate layer; the metal layer comprises a first surface and a second surface which are oppositely arranged, and the second surface of the metal layer is arranged on the substrate layer; the metal layer perforation assembly is arranged in the metal layer, the metal layer perforation assembly comprises a first conductor piece, a second conductor piece and a conductor connecting hole, the first conductor piece is formed on the first surface of the metal layer, the second conductor piece is formed on the second surface of the metal layer, and the conductor connecting hole is formed in the metal layer; the second conductor piece is connected to the first conductor piece through the conductor connecting hole; the substrate through hole is formed in the substrate layer; and the functional circuit is connected to at least one of the first conductor piece and the second conductor piece. According to the functional chip, the etching process difficulty is reduced, the occupied area of the metal layer is reduced, the resistance parasitic parameter and the capacitance parasitic parameter are reduced, the preparation period of the functional chip is shortened, and the production cost is reduced.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a functional chip for 3D chips. Background technique [0002] With the development of chip technology and the increasing demand for information technology, 3D chips are increasingly appearing in the integrated circuit industry. The 3D chip may include a plurality of functional chips arranged in a stack. Due to the needs of signal transmission, the signal connection lines in the 3D chip need to pass through the functional chips constituting the 3D chip. The connection of the signal line from the front to the back of the chip is realized through the entire chip through the through hole, and the TSV (Through Silicon Via) process is mainly used at present. [0003] Since TSVs need to penetrate the entire chip, TSVs not only need to penetrate various materials that make up the stacked circuit, but also need to penetrate a very thick silicon substrate. Etching tec...

AI Technical Summary

Problems solved by technology

At the same time, the diameter and length of the through-silicon vias are large, resulting in a very large chip area occupied by the through-silicon vias, large resistance parasitic parameters and capacitance parasitic parameters, long manufacturing cycle, and high cost.

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