Process for making double inlay structure for preventing positioning error

Abstract

The present invention provides one kind of double embedded structure making process. One low temperature chemical vapor deposition process, named DiRECT, is adopted to deposit one low temperature fluorocarbon film on one photoresist layer of limited double embedded structure. The fluorocarbon film is formed under the deposition condition lower than 100 deg.c, the photoresist layer will not be damaged and the intraconnection problem caused by the positioning error of the photoresist may be solved.

Description

technical field

[0001] The invention relates to a manufacturing method of a double damascene structure, in particular to a manufacturing method of a double damascene structure avoiding misalignment. Background technique

[0002] The dual damascene manufacturing process is a method that can simultaneously form a metal wire and a metal plug (plug) stacked structure in the dielectric layer. The dual damascene structure mainly includes an upper layer trench (trench) and a lower layer contact hole. (via hole), which is used to connect different components and wires between layers in a semiconductor chip, and use the surrounding inter-layer dielectrics (inter-layer dielectrics) to isolate it from other components. With the development of integrated circuits becoming increasingly sophisticated and complex, how to maintain the yield rate of the dual damascene structure is one of the important issues in the semiconductor manufacturing process.

[0003] Pleas...

Examples

Embodiment Construction

[0030] see Figure 4 to Figure 9 , Figure 4 to Figure 9 It is a schematic diagram of the method for fabricating a dual damascene structure on a semiconductor chip according to the present invention. Such as Figure 4 As shown, a semiconductor chip 20 includes a conductive layer substrate 22 , a passivation layer 24 formed on the conductive layer substrate 22 , and a dielectric layer 26 formed on the passivation layer 24 . First, a photoresist layer 28 is coated on the surface of the dielectric layer 26, and an opening is formed in the photoresist layer 28 through a photolithography process including exposure, development and cleaning. 28a to define the trench positions in the dual damascene structure. In a preferred embodiment of the present invention, the conductive layer base 22 is made of copper metal, and the dielectric layer 26 can be made of silicon oxide, fluorosilicate glass (FSG) or a dielectric material with a dielectric constant lower than 3 (such as SiLK TM ),...

technical field

[0001] The invention relates to a manufacturing method of a double damascene structure, in particular to a manufacturing method of a double damascene structure avoiding misalignment. Background technique

[0002] The dual damascene manufacturing process is a method that can simultaneously form a metal wire and a metal plug (plug) stacked structure in the dielectric layer. The dual damascene structure mainly includes an upper layer trench (trench) and a lower layer contact hole. (via hole), which is used to connect different components and wires between layers in a semiconductor chip, and use the surrounding inter-layer dielectrics (inter-layer dielectrics) to isolate it from other components. With the development of integrated circuits becoming increasingly sophisticated and complex, how to maintain the yield rate of the dual damascene structure is one of the important issues in the semiconductor manufacturing process.

[0003] Pleas...

Examples

Embodiment Construction

[0030] see Figure 4 to Figure 9 , Figure 4 to Figure 9 It is a schematic diagram of the method for fabricating a dual damascene structure on a semiconductor chip according to the present invention. Such as Figure 4 As shown, a semiconductor chip 20 includes a conductive layer substrate 22 , a passivation layer 24 formed on the conductive layer substrate 22 , and a dielectric layer 26 formed on the passivation layer 24 . First, a photoresist layer 28 is coated on the surface of the dielectric layer 26, and an opening is formed in the photoresist layer 28 through a photolithography process including exposure, development and cleaning. 28a to define the trench positions in the dual damascene structure. In a preferred embodiment of the present invention, the conductive layer base 22 is made of copper metal, and the dielectric layer 26 can be made of silicon oxide, fluorosilicate glass (FSG) or a dielectric material with a dielectric constant lower than 3 (such as SiLK TM ),...

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