Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Process for making double inlay structure for preventing positioning error

A technology of double damascene structure and manufacturing process, which is applied in the photolithographic process of pattern surface, semiconductor/solid-state device manufacturing, and photosensitive materials used in optomechanical equipment, etc., which can solve positioning errors and uneven photoresist thickness Equilibrium problem to achieve the effect of avoiding positioning errors

Inactive Publication Date: 2005-08-17
MACRONIX INT CO LTD
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] As mentioned above, when making the second opening 18a in the second photoresist layer 18, due to manufacturing process factors, such as photomask defects or uneven thickness of the photoresist, when the second opening 18a is defined A positioning error occurs such that a portion of the second opening 18a falls outside the trench in the first dielectric layer 16

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Process for making double inlay structure for preventing positioning error
  • Process for making double inlay structure for preventing positioning error
  • Process for making double inlay structure for preventing positioning error

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] see Figure 4 to Figure 9 , Figure 4 to Figure 9 It is a schematic diagram of the method for fabricating a dual damascene structure on a semiconductor chip according to the present invention. Such as Figure 4 As shown, a semiconductor chip 20 includes a conductive layer substrate 22 , a passivation layer 24 formed on the conductive layer substrate 22 , and a dielectric layer 26 formed on the passivation layer 24 . First, a photoresist layer 28 is coated on the surface of the dielectric layer 26, and an opening is formed in the photoresist layer 28 through a photolithography process including exposure, development and cleaning. 28a to define the trench positions in the dual damascene structure. In a preferred embodiment of the present invention, the conductive layer base 22 is made of copper metal, and the dielectric layer 26 can be made of silicon oxide, fluorosilicate glass (FSG) or a dielectric material with a dielectric constant lower than 3 (such as SiLK TM ),...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
poweraaaaaaaaaa
Login to View More

Abstract

The present invention provides one kind of double embedded structure making process. One low temperature chemical vapor deposition process, named DiRECT, is adopted to deposit one low temperature fluorocarbon film on one photoresist layer of limited double embedded structure. The fluorocarbon film is formed under the deposition condition lower than 100 deg.c, the photoresist layer will not be damaged and the intraconnection problem caused by the positioning error of the photoresist may be solved.

Description

technical field [0001] The invention relates to a manufacturing method of a double damascene structure, in particular to a manufacturing method of a double damascene structure avoiding misalignment. Background technique [0002] The dual damascene manufacturing process is a method that can simultaneously form a metal wire and a metal plug (plug) stacked structure in the dielectric layer. The dual damascene structure mainly includes an upper layer trench (trench) and a lower layer contact hole. (via hole), which is used to connect different components and wires between layers in a semiconductor chip, and use the surrounding inter-layer dielectrics (inter-layer dielectrics) to isolate it from other components. With the development of integrated circuits becoming increasingly sophisticated and complex, how to maintain the yield rate of the dual damascene structure is one of the important issues in the semiconductor manufacturing process. [0003] Pleas...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/00G03F7/09G03F7/26
Inventor 钟嘉麒薛正诚
Owner MACRONIX INT CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com