Memory equipment having page buffer storage with double-register and its use thereof

Abstract

A memory device has an array of memory cells to store data, and a Y-gating circuit to gate data stored in a group of the memory cells. A page buffer is coupled between the memory cell array and the Y-gating circuit. The page buffer includes a dual register corresponding to each memory cell of the group. The dual register includes a first register and an associated second register. The first and second registers are adapted to exchange data with each other, with cells of the memory cell array, and with the Y-gating circuit.

Description

[0001] This application claims priority to US Provisional Application No. 60 / 307572, filed July 23, 2001, which is hereby incorporated by reference. technical field [0002] The present invention relates to the field of semiconductor memory devices, more specifically flash memory devices having a page buffer circuit with double registers. Background technique [0003] Recent trends in semiconductor memory devices are high integration, large capacity, and support for high-speed system operation. These trends are equally directed to volatile memory (eg, dynamic random access memory (DRAM) and static random access memory (SRAM)) and nonvolatile memory (eg, flash memory). [0004] Flash memory is generally classified into a Not-NOR (NOR) type flash memory and a Not-NAND (NAND) type flash memory. NOR type flash memory is used in applications where small amounts of information must be read out of sequence at high speed, while ...

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Problems solved by technology

Therefore, the loading time greatly affects the information storage characteristics of NAND type flash memory

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