Electric interconnecting structure on substrate and producing method thereof

Abstract

An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Description

technical field [0001] This invention relates to interconnect structures for high speed microprocessors, application specific integrated circuits (ASICs) and high speed IC's. More specifically, the present invention provides low or ultra-low dielectric constant (k) interconnect structures that increase circuit speed, accurate value of conductor resistance, and improve mechanical integrity. Background technique [0002] Many dual damascene low-k dielectric plus Cu interconnect structures are known. Such as dual damascene process, where SiLK TM For use as a low-k dielectric material, see US Patent 6,383,920, assigned to the same assignee as the present invention and incorporated by reference in its entirety as if fully set forth herein. [0003] The integration of low and ultra-low dielectric constant (k) materials requires a chemical mechanical planarization (CMP) polish stop layer in order to protect the underlying dielectric and prevent corrosion and dishing of low-k diel...

AI Technical Summary

Problems solved by technology

Therefore, higher permittivity materials (typically SiC with k=4.1) must remain in the structure, resulting in an increase in the effective permittivity

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