Single-electron storage designed based on coulomb damping principle and its preparing method

A principle design, Coulomb blocking technology, applied in the direction of electric solid-state devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of low operating temperature of storage devices, high power consumption of devices, and restrictions on the further improvement of integration

Inactive Publication Date: 2004-02-11
INST OF PHYSICS - CHINESE ACAD OF SCI
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  • Claims
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Problems solved by technology

[0004] The purpose of the present invention is to solve the difficulties faced by the development of traditional memory and single electron memory, overcome the existing MTJ/MOSFET structure memory, limit the defect of further improvement of integration; low, resulting in very low operating temperature of the sto...

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  • Single-electron storage designed based on coulomb damping principle and its preparing method
  • Single-electron storage designed based on coulomb damping principle and its preparing method
  • Single-electron storage designed based on coulomb damping principle and its preparing method

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Embodiment 2

[0030] The preparation method of the source electrode 3, the drain electrode 4 and the gate electrode 5 is the same as that of embodiment 1, except that the thickness of the silicon layer on the surface of the SOI after thinning is 5 or 500 nanometers; the source The distance between the pole electrode and the drain electrode is 5 nanometers or 1 micrometer; the gate area is between 1 square nanometer and 1 square micrometer. And on the inner side of the drain electrode 4 and the outer side of the gate electrode 5, a catalyst region 13 is placed, and the catalyst region 13 is made of Fe, Co, Ni or an alloy thereof, such as Figure 9 As shown, carbon nanotubes are grown in situ toward the direction of the source electrode 3 , and the other end of the grown carbon nanotubes is in contact with the source electrode 3 . In addition, the probe technology of the atomic force microscope is used to deform the carbon nanotube 7 locally to form a tunnel junction 8 with a distance of 10 n...

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Abstract

This invention relates to a single electron memory and it spreparation method designed on coulomb damping theory including a monocrystal silicon layer on the surface with SOI as the substrate to be doped and etched to a carbon nm transistor structure containing an electrode as the source, an electrode as the drain and a grid, a single wall carbon nanometer tube is set on the two electrodes to form ohmic contact, the grid is between the two electrodes and at a side of the carbon nm tube, the other tube with more than two tunnel through joints is set on the grid and the source or grain of the transister to form ohmic contact. The said device is easy to be prepared.

Description

technical field [0001] The invention belongs to a single-electron memory device, in particular to a single-electron memory with low power consumption that can work at room temperature and a preparation method thereof designed and prepared by utilizing the Coulomb blocking effect of nanowires with a multi-quantum dot structure. Background technique [0002] Memory accounts for 40% of the world's semiconductor market. Semiconductor products other than memory are updated every 2 years, while memory is a generation every 18 months. Taking the development of dynamic memory (DRAM) as an example, in 1988 Japan The line width of the lines on the silicon chip reached 0.8 microns, and the 4Mb DRAM came out, thus entering the era of ultra-large-scale integration ULSI; in 1992, the 16Mb chip with a line width of 0.5 microns was put into production; in 1994, the 64Mb chip with a line width of 0.35 microns was launched. Chip production; 0.13-micron 4Gb DRAM will soon be realized. However...

Claims

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Application Information

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IPC IPC(8): H01L21/84H01L27/12
Inventor 孙劲鹏王太宏
Owner INST OF PHYSICS - CHINESE ACAD OF SCI
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